Testboard GUI![]() | Source code and usage instructions for the GUI to control the testboard |
Testboard Analysis![]() | Scripts for analyzing data taken with testboard, particularly pedestal data and data taken using the onboard pulser |
Document | Description |
datasheet_Lauroc1_20190506.pdf | Documentation for the LAUROC1 pre-amp/shaper. Updated May 6, 2019 |
COLUTAV2_ds.pdf | Documentation for the COLUTAv2 ADC. Updated February 2, 2019 |
lpGBT.pdf | Documentation for the low power Giga-Bit Transceiver. Updated April 9, 2019 |
dac9881.pdf | Documentation for the DAC that provides a voltage to the onboard pulser. Updated September 2016 |
a10_overview.pdf a10_datasheet.pdf | Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB |
Si5345-44-42-D-RM.pdf | Documentation for onboard Si5345 Clock Chip |
File | Comment |
Analog_Testboard_FPGA_oct2.zip | v1.1 board firmware as of Oct 2, 2019 |
Analog_Testboard.zip | v1.1 board schematic (.pdf, .pcb, and .sch) |
Board Number | Location |
E149372 | Nevis |
E149373 | Saclay |
E149374 | Nevis |
E149375 | BNL |
E149376 | Orsay |
E149377 | UT Austin |
Symptom:
3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.
Symptom:
4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).
I | Attachment | History | Action | Size | Date | Who | Comment |
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20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf | r1 | manage | 25.6 K | 2019-10-04 - 19:24 | BrianKirby | |
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20191007_atb_howtoProgFW_1.png | r1 | manage | 1071.1 K | 2019-10-07 - 19:13 | BrianKirby | |
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Analog_Testboard.zip | r1 | manage | 3465.6 K | 2019-09-30 - 14:39 | DanielWilliams | Analog Testboard v1.1 schematic |
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Analog_Testboard_FPGA_oct2.zip | r1 | manage | 24973.5 K | 2019-10-02 - 20:18 | DanielWilliams | Analog Testboard v1.1 firmware as of Oct 2, 2019 |
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Analog_Testboard_FPGA_sept24.zip | r1 | manage | 25014.7 K | 2019-09-27 - 19:39 | BrianKirby | Analog Testboard v1.1 firmware project as of Sept 24, 2019 |
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COLUTAV2_ds.pdf | r1 | manage | 743.0 K | 2019-09-26 - 19:24 | DanielWilliams | |
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DAC_linearity_zoom.png | r1 | manage | 28.2 K | 2019-09-30 - 19:46 | JuliaGonski | |
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Nonlinearity_percent_differential_low_gain.png | r1 | manage | 28.8 K | 2019-09-30 - 20:40 | JuliaGonski | |
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Power_mezzanine.zip | r1 | manage | 5828.2 K | 2022-07-26 - 17:13 | JaroslavBan | |
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Si5345-44-42-D-RM.pdf | r1 | manage | 2049.3 K | 2019-12-16 - 17:13 | DanielWilliams | |
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a10_datasheet.pdf | r1 | manage | 959.9 K | 2019-09-26 - 19:58 | DanielWilliams | |
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a10_overview.pdf | r1 | manage | 503.8 K | 2019-09-26 - 19:58 | DanielWilliams | |
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dac9881.pdf | r1 | manage | 2824.6 K | 2019-09-26 - 19:24 | DanielWilliams | |
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datasheet_Lauroc1_20190506.pdf | r1 | manage | 1568.4 K | 2019-09-26 - 19:24 | DanielWilliams | |
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hist_pedestal_ADC2_Channel1.pdf | r1 | manage | 191.5 K | 2019-09-30 - 20:33 | JuliaGonski | |
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hist_pedestal_ADC2_Channel1.png | r1 | manage | 17.8 K | 2019-09-30 - 20:34 | JuliaGonski | |
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image_2019_10_14T15_18_50_121Z.png | r1 | manage | 63.1 K | 2019-10-14 - 15:21 | JuliaGonski | |
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lpGBT.pdf | r1 | manage | 5373.7 K | 2019-09-26 - 19:24 | DanielWilliams |