June 2021 eLog

2021-06-14

Author: Colin

  • Encountering once again the same issues from the 2021-01-20 eLog.
    • Traceback (most recent call last):
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/serial/serialposix.py", line 265, in open
          self.fd = os.open(self.portstr, os.O_RDWR | os.O_NOCTTY | os.O_NONBLOCK)
      PermissionError: [Errno 13] Permission denied: '/dev/ttyACM0'
      
      During handling of the above exception, another exception occurred:
      
      Traceback (most recent call last):
        File "<stdin>", line 1, in <module>
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/dcps/SCPI.py", line 69, in open
          self._inst = self._rm.open_resource(self._resource,
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/pyvisa/highlevel.py", line 1771, in open_resource
          res.open(access_mode, open_timeout)
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/pyvisa/resources/resource.py", line 218, in open
          self.session, status = self._resource_manager.open_bare_resource(self._resource_name, access_mode, open_timeout)
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/pyvisa/highlevel.py", line 1725, in open_bare_resource
          return self.visalib.open(self.session, resource_name, access_mode, open_timeout)
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/pyvisa-py/highlevel.py", line 194, in open
          sess = cls(session, resource_name, parsed, open_timeout)
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/pyvisa-py/sessions.py", line 218, in __init__
          self.after_parsing()
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/pyvisa-py/serial.py", line 65, in after_parsing
          self.interface = cls(port=self.parsed.board, timeout=self.timeout, write_timeout=self.timeout)
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/serial/serialutil.py", line 240, in __init__
          self.open()
        File "/home/ctalab/anaconda3/envs/cta/lib/python3.8/site-packages/serial/serialposix.py", line 268, in open
          raise SerialException(msg.errno, "could not open port {}: {}".format(self._port, msg))
      serial.serialutil.SerialException: [Errno 13] could not open port /dev/ttyACM0: [Errno 13] Permission denied: '/dev/ttyACM0'
    • Going to try and use the second option from this answer on stack overflow: https://stackoverflow.com/a/27886201
      • Added it in at: /etc/udev/rules.d/serial-ports.rules
      • This seems to have resolved the problem
  • Starting to build up the base of the gui at /home/ctalab/software/control_guis/obj_flasher_gui.py

2021-06-10

Author: Massimo

  • Performed a visual inspection with Nancy's microscope of all the components on the board, no apparent signs of broken pieces (cracks, burns...)
  • Talked to Leonardo, neither he nor Francesco L. have any better idea of what could have possibly failed; they'll try to find a spare board, re-program the FPGA and send it to us

2021-06-09

Author: Massimo with support from Ray

  • We replaced the ADP3338 again, but there still is a short between Vout (which should be 3.3V) and ground. We then removed the ADP3338 and checked (short still there) the first immediate components downstream of the 3.3V
    • FC06
    • U3
    • FC01
  • Nothing helped
  • Asked Francesco L. for extra ideas and otherwise for spare board

2021-06-08

Author: Massimo

  • Replaced U6 with new ADP3338; the power supply immediately reaches compliance, lowering voltage from input 5V to 2V roughly. Also, ADP338 immediately starts heating up, there is still a short somewhere. Check capacitors FC05/6?

-- Massimo Capasso - 2021-06-08

Comments


This topic: Veritas > PSCT > NevisLabsSetup > NevisLabsELog > NevisLabsELogJune2021
Topic revision: r4 - 2021-06-14 - ColinAdams
 
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