Difference: AnalogTestboard (9 vs. 10)

Revision 102019-10-14 - JuliaGonski

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Changed:
<
<

>
>


 

Git Repositories

Testboard GUI Source code and usage instructions for the GUI to control the testboard
Testboard Analysis Scripts for analyzing data taken with testboard, particularly pedestal data and data taken using the onboard pulser
Line: 27 to 26
 a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB

Board Firmware and Schematic

Changed:
<
<
File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)

Location of connector to program FPGA configuration memory device shown here.
>
>
File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)

Location of connector to program FPGA configuration memory device shown here.
 


Board Specific Pages

Board Number Location
E149372 Nevis
Line: 46 to 44
 DAC_linearity_zoom.png

2. Even/Odd ADC. All ADCs have a preference for the LSB to have a value of 1, resulting in more odd ADC count values than even. Extent of this preference is very dependent on the values of pots P15 and P16, which control the positive and negative reference voltages of the SAR.

Changed:
<
<
  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V

>
>
  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V

 Symptom:

hist_pedestal_ADC2_Channel1.png

Line: 58 to 55
  Nonlinearity_percent_differential_low_gain.png
Changed:
<
<

--
Daniel Williams - 2019-09-26
>
>
4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

Symptom:

image_2019_10_14T15_18_50_121Z.png

--

Daniel Williams - 2019-09-26

 

Comments

Changed:
<
<

<--/commentPlugin-->
>
>


<--/commentPlugin-->
 
META FILEATTACHMENT attachment="COLUTAV2_ds.pdf" attr="" comment="" date="1569525865" name="COLUTAV2_ds.pdf" path="COLUTAV2_ds.pdf" size="760844" user="DanielWilliams" version="1"
META FILEATTACHMENT attachment="dac9881.pdf" attr="" comment="" date="1569525865" name="dac9881.pdf" path="dac9881.pdf" size="2892441" user="DanielWilliams" version="1"
Line: 80 to 81
 
META FILEATTACHMENT attachment="Analog_Testboard_FPGA_oct2.zip" attr="" comment="Analog Testboard v1.1 firmware as of Oct 2, 2019" date="1570047491" name="Analog_Testboard_FPGA_oct2.zip" path="Analog_Testboard_FPGA_oct2.zip" size="25572903" user="DanielWilliams" version="1"
META FILEATTACHMENT attachment="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" attr="" comment="" date="1570217096" name="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" path="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" size="26229" user="BrianKirby" version="1"
META FILEATTACHMENT attachment="20191007_atb_howtoProgFW_1.png" attr="" comment="" date="1570475583" name="20191007_atb_howtoProgFW_1.png" path="20191007_atb_howtoProgFW_1.png" size="1096843" user="BrianKirby" version="1"
Added:
>
>
META FILEATTACHMENT attachment="image_2019_10_14T15_18_50_121Z.png" attr="" comment="" date="1571066483" name="image_2019_10_14T15_18_50_121Z.png" path="image_2019_10_14T15_18_50_121Z.png" size="64574" user="JuliaGonski" version="1"
 
This site is powered by the TWiki collaboration platform Powered by PerlCopyright © 2008-2020 by the contributing authors. All material on this collaboration platform is the property of the contributing authors.
Ideas, requests, problems regarding TWiki? Send feedback