Difference: AnalogTestboard (1 vs. 15)

Revision 152022-07-26 - JaroslavBan

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 82 to 82
 
META FILEATTACHMENT attachment="20191007_atb_howtoProgFW_1.png" attr="" comment="" date="1570475583" name="20191007_atb_howtoProgFW_1.png" path="20191007_atb_howtoProgFW_1.png" size="1096843" user="BrianKirby" version="1"
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META FILEATTACHMENT attachment="Si5345-44-42-D-RM.pdf" attr="" comment="" date="1576516400" name="Si5345-44-42-D-RM.pdf" path="Si5345-44-42-D-RM.pdf" size="2098472" user="DanielWilliams" version="1"
Added:
>
>
META FILEATTACHMENT attachment="Power_mezzanine.zip" attr="" comment="" date="1658855615" name="Power_mezzanine.zip" path="Power_mezzanine.zip" size="5968028" user="JaroslavBan" version="1"

Revision 142022-06-28 - BrianKirby

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 24 to 24
 a10_overview.pdf

a10_datasheet.pdf

Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB
Si5345-44-42-D-RM.pdf Documentation for onboard Si5345 Clock Chip
Added:
>
>

Presentations

ATLAS Upgrade Week Nov 2019

 

Board Firmware and Schematic

File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)
Location of connector to program FPGA configuration memory device shown here.
Line: 50 to 53
  3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.

Symptom:

Nonlinearity_percent_differential_low_gain.png

Changed:
<
<		 4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

>
>		 4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

  Symptom:

Revision 132020-05-11 - DanielWilliams

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 23 to 23
  a10_overview.pdf
Changed:
<
<		a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB
Si5345-44-42-D-RM.pdf Documentation for onboard Si5345 Clock Chip
>
>		a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB
Si5345-44-42-D-RM.pdf Documentation for onboard Si5345 Clock Chip
 

Board Firmware and Schematic

File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)
Location of connector to program FPGA configuration memory device shown here.


Board Specific Pages

Board Number Location
E149372 Nevis
Changed:
<
<
E149373 Nevis
>
>
E149373 Saclay
 
E149374 Nevis
E149375 BNL
Changed:
<
<
E149376 Nevis
E149377 Nevis
>
>
E149376 Orsay
E149377 UT Austin
 

Known Issues

1. DAC Turn On. All DAC settings below a particular turn on point correspond to the same measured test point voltage (7.7-8 mV). Turn on point varies for different boards (typically around 400-600).

Line: 51 to 50
  3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.

Symptom:

Nonlinearity_percent_differential_low_gain.png

Changed:
<
<		 4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

>
>		 4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

  Symptom:

Revision 122019-12-16 - DanielWilliams

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 23 to 23
  a10_overview.pdf
Changed:
<
<		a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB
>
>		a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB
Si5345-44-42-D-RM.pdf Documentation for onboard Si5345 Clock Chip
 

Board Firmware and Schematic

File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)
Location of connector to program FPGA configuration memory device shown here.
Line: 50 to 51
  3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.

Symptom:

Nonlinearity_percent_differential_low_gain.png

Changed:
<
<		 4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

>
>		 4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

  Symptom:
Line: 59 to 60
 --

Daniel Williams - 2019-09-26

Comments

Changed:
<
<		 

<--/commentPlugin-->
>
>		 

<--/commentPlugin-->
 
META FILEATTACHMENT attachment="COLUTAV2_ds.pdf" attr="" comment="" date="1569525865" name="COLUTAV2_ds.pdf" path="COLUTAV2_ds.pdf" size="760844" user="DanielWilliams" version="1"
META FILEATTACHMENT attachment="dac9881.pdf" attr="" comment="" date="1569525865" name="dac9881.pdf" path="dac9881.pdf" size="2892441" user="DanielWilliams" version="1"
Line: 77 to 79
 
META FILEATTACHMENT attachment="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" attr="" comment="" date="1570217096" name="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" path="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" size="26229" user="BrianKirby" version="1"
META FILEATTACHMENT attachment="20191007_atb_howtoProgFW_1.png" attr="" comment="" date="1570475583" name="20191007_atb_howtoProgFW_1.png" path="20191007_atb_howtoProgFW_1.png" size="1096843" user="BrianKirby" version="1"
META FILEATTACHMENT attachment="image_2019_10_14T15_18_50_121Z.png" attr="" comment="" date="1571066483" name="image_2019_10_14T15_18_50_121Z.png" path="image_2019_10_14T15_18_50_121Z.png" size="64574" user="JuliaGonski" version="1"
Added:
>
>
META FILEATTACHMENT attachment="Si5345-44-42-D-RM.pdf" attr="" comment="" date="1576516400" name="Si5345-44-42-D-RM.pdf" path="Si5345-44-42-D-RM.pdf" size="2098472" user="DanielWilliams" version="1"

Revision 112019-10-14 - DanielWilliams

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 31 to 31
 
Board Number Location
E149372 Nevis
E149373 Nevis
Changed:
<
<
E149374 Nevis
>
>
E149374 Nevis
 
E149375 BNL
E149376 Nevis
E149377 Nevis
Line: 45 to 45
  2. Even/Odd ADC. All ADCs have a preference for the LSB to have a value of 1, resulting in more odd ADC count values than even. Extent of this preference is very dependent on the values of pots P15 and P16, which control the positive and negative reference voltages of the SAR.
  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V

Changed:
<
<		 Symptom:

hist_pedestal_ADC2_Channel1.png

3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.

Symptom:

Nonlinearity_percent_differential_low_gain.png

4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

>
>		 Symptom:

hist_pedestal_ADC2_Channel1.png

3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.

Symptom:

Nonlinearity_percent_differential_low_gain.png

4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

  Symptom:

Revision 102019-10-14 - JuliaGonski

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Changed:
<
<
>
>

 

Git Repositories

Testboard GUI Source code and usage instructions for the GUI to control the testboard
Testboard Analysis Scripts for analyzing data taken with testboard, particularly pedestal data and data taken using the onboard pulser
Line: 27 to 26
 a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB

Board Firmware and Schematic

Changed:
<
<
File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)
Location of connector to program FPGA configuration memory device shown here.
>
>
File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)
Location of connector to program FPGA configuration memory device shown here.
 


Board Specific Pages

Board Number Location
E149372 Nevis
Line: 46 to 44
 DAC_linearity_zoom.png

2. Even/Odd ADC. All ADCs have a preference for the LSB to have a value of 1, resulting in more odd ADC count values than even. Extent of this preference is very dependent on the values of pots P15 and P16, which control the positive and negative reference voltages of the SAR.

Changed:
<
<
  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V

>
>
  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V

 Symptom:

hist_pedestal_ADC2_Channel1.png

Line: 58 to 55
  Nonlinearity_percent_differential_low_gain.png
Changed:
<
<
--
Daniel Williams - 2019-09-26
>
>		 4. DAC Stuck/Misaligned. When powering up, or occasionally during operation, the DAC will get stuck in a bad operational state. This is indicated by the DAC readback function, which checks the equality of the SPI instruction that is sent and readback. If the following error comes up during data-taking, it is recommended to power cycle the board (resetting the DAC).

Symptom:

image_2019_10_14T15_18_50_121Z.png

--

Daniel Williams - 2019-09-26

 

Comments

Changed:
<
<
<--/commentPlugin-->
>
>		 

<--/commentPlugin-->
 
META FILEATTACHMENT attachment="COLUTAV2_ds.pdf" attr="" comment="" date="1569525865" name="COLUTAV2_ds.pdf" path="COLUTAV2_ds.pdf" size="760844" user="DanielWilliams" version="1"
META FILEATTACHMENT attachment="dac9881.pdf" attr="" comment="" date="1569525865" name="dac9881.pdf" path="dac9881.pdf" size="2892441" user="DanielWilliams" version="1"
Line: 80 to 81
 
META FILEATTACHMENT attachment="Analog_Testboard_FPGA_oct2.zip" attr="" comment="Analog Testboard v1.1 firmware as of Oct 2, 2019" date="1570047491" name="Analog_Testboard_FPGA_oct2.zip" path="Analog_Testboard_FPGA_oct2.zip" size="25572903" user="DanielWilliams" version="1"
META FILEATTACHMENT attachment="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" attr="" comment="" date="1570217096" name="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" path="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" size="26229" user="BrianKirby" version="1"
META FILEATTACHMENT attachment="20191007_atb_howtoProgFW_1.png" attr="" comment="" date="1570475583" name="20191007_atb_howtoProgFW_1.png" path="20191007_atb_howtoProgFW_1.png" size="1096843" user="BrianKirby" version="1"
Added:
>
>
META FILEATTACHMENT attachment="image_2019_10_14T15_18_50_121Z.png" attr="" comment="" date="1571066483" name="image_2019_10_14T15_18_50_121Z.png" path="image_2019_10_14T15_18_50_121Z.png" size="64574" user="JuliaGonski" version="1"

Revision 92019-10-07 - DanielWilliams

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 33 to 33
 
Board Number Location
E149372 Nevis
E149373 Nevis
Changed:
<
<
E149374 Nevis
>
>
E149374 Nevis
 
E149375 BNL
E149376 Nevis
E149377 Nevis
Line: 46 to 46
 DAC_linearity_zoom.png

2. Even/Odd ADC. All ADCs have a preference for the LSB to have a value of 1, resulting in more odd ADC count values than even. Extent of this preference is very dependent on the values of pots P15 and P16, which control the positive and negative reference voltages of the SAR.

Changed:
<
<
  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V

>
>
  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V

  Symptom:
Line: 59 to 59
 Nonlinearity_percent_differential_low_gain.png


--

Changed:
<
<		 Daniel Williams - 2019-09-26
>
>		 Daniel Williams - 2019-09-26
 

Comments


Revision 82019-10-07 - BrianKirby

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Changed:
<
<
>
>
 

Git Repositories

Testboard GUI Source code and usage instructions for the GUI to control the testboard
Testboard Analysis Scripts for analyzing data taken with testboard, particularly pedestal data and data taken using the onboard pulser
Line: 26 to 27
 a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB

Board Firmware and Schematic

Changed:
<
<
File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)

Board Specific Pages

>
>
File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)
Location of connector to program FPGA configuration memory device shown here.


Board Specific Pages

 
Board Number Location
E149372 Nevis
E149373 Nevis
Line: 45 to 46
  DAC_linearity_zoom.png

2. Even/Odd ADC. All ADCs have a preference for the LSB to have a value of 1, resulting in more odd ADC count values than even. Extent of this preference is very dependent on the values of pots P15 and P16, which control the positive and negative reference voltages of the SAR.

Changed:
<
<
  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V
>
>
  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V

  Symptom:
Line: 57 to 58
  Nonlinearity_percent_differential_low_gain.png
Changed:
<
<
--
Daniel Williams - 2019-09-26
>
>
--
Daniel Williams - 2019-09-26
 

Comments

Changed:
<
<		 
<--/commentPlugin-->
>
>
<--/commentPlugin-->
 
META FILEATTACHMENT attachment="COLUTAV2_ds.pdf" attr="" comment="" date="1569525865" name="COLUTAV2_ds.pdf" path="COLUTAV2_ds.pdf" size="760844" user="DanielWilliams" version="1"
META FILEATTACHMENT attachment="dac9881.pdf" attr="" comment="" date="1569525865" name="dac9881.pdf" path="dac9881.pdf" size="2892441" user="DanielWilliams" version="1"
Line: 76 to 79
 
META FILEATTACHMENT attachment="Nonlinearity_percent_differential_low_gain.png" attr="" comment="" date="1569876050" name="Nonlinearity_percent_differential_low_gain.png" path="Nonlinearity_percent_differential_low_gain.png" size="29510" user="JuliaGonski" version="1"
META FILEATTACHMENT attachment="Analog_Testboard_FPGA_oct2.zip" attr="" comment="Analog Testboard v1.1 firmware as of Oct 2, 2019" date="1570047491" name="Analog_Testboard_FPGA_oct2.zip" path="Analog_Testboard_FPGA_oct2.zip" size="25572903" user="DanielWilliams" version="1"
META FILEATTACHMENT attachment="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" attr="" comment="" date="1570217096" name="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" path="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" size="26229" user="BrianKirby" version="1"
Added:
>
>
META FILEATTACHMENT attachment="20191007_atb_howtoProgFW_1.png" attr="" comment="" date="1570475583" name="20191007_atb_howtoProgFW_1.png" path="20191007_atb_howtoProgFW_1.png" size="1096843" user="BrianKirby" version="1"

Revision 72019-10-04 - BrianKirby

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 75 to 75
 
META FILEATTACHMENT attachment="hist_pedestal_ADC2_Channel1.png" attr="" comment="" date="1569875677" name="hist_pedestal_ADC2_Channel1.png" path="hist_pedestal_ADC2_Channel1.png" size="18180" user="JuliaGonski" version="1"
META FILEATTACHMENT attachment="Nonlinearity_percent_differential_low_gain.png" attr="" comment="" date="1569876050" name="Nonlinearity_percent_differential_low_gain.png" path="Nonlinearity_percent_differential_low_gain.png" size="29510" user="JuliaGonski" version="1"
META FILEATTACHMENT attachment="Analog_Testboard_FPGA_oct2.zip" attr="" comment="Analog Testboard v1.1 firmware as of Oct 2, 2019" date="1570047491" name="Analog_Testboard_FPGA_oct2.zip" path="Analog_Testboard_FPGA_oct2.zip" size="25572903" user="DanielWilliams" version="1"
Added:
>
>
META FILEATTACHMENT attachment="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" attr="" comment="" date="1570217096" name="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" path="20190926_TPVvsDAC_allATB_v1p1_-_Sheet1.pdf" size="26229" user="BrianKirby" version="1"

Revision 62019-10-02 - DanielWilliams

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 26 to 26
 a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB

Board Firmware and Schematic

Changed:
<
<
File Comment
Analog_Testboard_FPGA_sept24.zip v1.1 board firmware as of Sept 24, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)
>
>
File Comment
Analog_Testboard_FPGA_oct2.zip v1.1 board firmware as of Oct 2, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)
 

Board Specific Pages

Board Number Location
Line: 50 to 51
  hist_pedestal_ADC2_Channel1.png
Changed:
<
<		 3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.
>
>		 3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.
  Symptom:
Line: 73 to 74
 
META FILEATTACHMENT attachment="hist_pedestal_ADC2_Channel1.pdf" attr="" comment="" date="1569875626" name="hist_pedestal_ADC2_Channel1.pdf" path="hist_pedestal_ADC2_Channel1.pdf" size="196072" user="JuliaGonski" version="1"
META FILEATTACHMENT attachment="hist_pedestal_ADC2_Channel1.png" attr="" comment="" date="1569875677" name="hist_pedestal_ADC2_Channel1.png" path="hist_pedestal_ADC2_Channel1.png" size="18180" user="JuliaGonski" version="1"
META FILEATTACHMENT attachment="Nonlinearity_percent_differential_low_gain.png" attr="" comment="" date="1569876050" name="Nonlinearity_percent_differential_low_gain.png" path="Nonlinearity_percent_differential_low_gain.png" size="29510" user="JuliaGonski" version="1"
Added:
>
>
META FILEATTACHMENT attachment="Analog_Testboard_FPGA_oct2.zip" attr="" comment="Analog Testboard v1.1 firmware as of Oct 2, 2019" date="1570047491" name="Analog_Testboard_FPGA_oct2.zip" path="Analog_Testboard_FPGA_oct2.zip" size="25572903" user="DanielWilliams" version="1"

Revision 52019-09-30 - JuliaGonski

Line: 1 to 1
 

Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Added:
>
>
 

Git Repositories

Testboard GUI Source code and usage instructions for the GUI to control the testboard
Testboard Analysis Scripts for analyzing data taken with testboard, particularly pedestal data and data taken using the onboard pulser
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-- Daniel Williams - 2019-09-26
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Known Issues

1. DAC Turn On. All DAC settings below a particular turn on point correspond to the same measured test point voltage (7.7-8 mV). Turn on point varies for different boards (typically around 400-600).

Symptom:

DAC_linearity_zoom.png

2. Even/Odd ADC. All ADCs have a preference for the LSB to have a value of 1, resulting in more odd ADC count values than even. Extent of this preference is very dependent on the values of pots P15 and P16, which control the positive and negative reference voltages of the SAR.

  • Should have: VREFN_SAR = 0.1, VREFP_SAR 1.1V
Symptom:

hist_pedestal_ADC2_Channel1.png

3. Clock Feedthrough (CFT). Pulses from on board pulser contain an extra injected charge that comes from clock signal passing through analog switch. This "clock feedthrough" does not scale with DAC setting and is not expected to have a shape that is the same as that of the pulse. As a result, all pulses are a sum of the true pulse shape and this CFT offset, distorting the shape and affecting the linearity of the pulse height to DAC setting. This is particularly noticeable at the lowest DAC settings, where the CFT constitutes a significant fraction of the total pulse.

Symptom:

Nonlinearity_percent_differential_low_gain.png


--
Daniel Williams - 2019-09-26

 

Comments

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Revision 42019-09-30 - DanielWilliams

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Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

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 a10_overview.pdf

a10_datasheet.pdf

Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB
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Firmware

Firmware Project File Comment
Analog_Testboard_FPGA_sept24.zip v1.1 board firmware as of Sept 24, 2019
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Board Firmware and Schematic

 
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File Comment
Analog_Testboard_FPGA_sept24.zip v1.1 board firmware as of Sept 24, 2019
Analog_Testboard.zip v1.1 board schematic (.pdf, .pcb, and .sch)
 

Board Specific Pages

Board Number Location
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META FILEATTACHMENT attachment="Analog_Testboard_FPGA_sept24.zip" attr="" comment="Analog Testboard v1.1 firmware project as of Sept 24, 2019" date="1569613152" name="Analog_Testboard_FPGA_sept24.zip" path="Analog_Testboard_FPGA_sept24.zip" size="25615056" user="BrianKirby" version="1"
META FILEATTACHMENT attachment="a10_datasheet.pdf" attr="" comment="" date="1569527912" name="a10_datasheet.pdf" path="a10_datasheet.pdf" size="982908" user="DanielWilliams" version="1"
META FILEATTACHMENT attachment="a10_overview.pdf" attr="" comment="" date="1569527912" name="a10_overview.pdf" path="a10_overview.pdf" size="515933" user="DanielWilliams" version="1"
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Revision 32019-09-27 - BrianKirby

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Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 23 to 23
 a10_overview.pdf

a10_datasheet.pdf

Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB
Added:
>
>

Firmware

Firmware Project File Comment
Analog_Testboard_FPGA_sept24.zip v1.1 board firmware as of Sept 24, 2019
 

Board Specific Pages

Board Number Location
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E149375 BNL
E149376 Nevis
E149377 Nevis
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-- Daniel Williams - 2019-09-26
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-- Daniel Williams - 2019-09-26
 

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META FILEATTACHMENT attachment="COLUTAV2_ds.pdf" attr="" comment="" date="1569525865" name="COLUTAV2_ds.pdf" path="COLUTAV2_ds.pdf" size="760844" user="DanielWilliams" version="1"
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META FILEATTACHMENT attachment="Analog_Testboard_FPGA_sept24.zip" attr="" comment="Analog Testboard v1.1 firmware project as of Sept 24, 2019" date="1569613152" name="Analog_Testboard_FPGA_sept24.zip" path="Analog_Testboard_FPGA_sept24.zip" size="25615056" user="BrianKirby" version="1"
 
META FILEATTACHMENT attachment="a10_datasheet.pdf" attr="" comment="" date="1569527912" name="a10_datasheet.pdf" path="a10_datasheet.pdf" size="982908" user="DanielWilliams" version="1"
META FILEATTACHMENT attachment="a10_overview.pdf" attr="" comment="" date="1569527912" name="a10_overview.pdf" path="a10_overview.pdf" size="515933" user="DanielWilliams" version="1"

Revision 22019-09-27 - DanielWilliams

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Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Line: 22 to 22
  a10_overview.pdf
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<		a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB


-- Daniel Williams - 2019-09-26
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>		a10_datasheet.pdf
Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB

Board Specific Pages

Board Number Location
E149372 Nevis
E149373 Nevis
E149374 Nevis
E149375 BNL
E149376 Nevis
E149377 Nevis


-- Daniel Williams - 2019-09-26
 

Comments 


<--/commentPlugin-->

Revision 12019-09-26 - DanielWilliams

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Added:
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Analog Testboard

This TWiki aims to gather all resources regarding the analog testboard, an integration test of the readout electronics for the High-Luminosity LHC upgrade to the ATLAS Liquid Argon calorimeter.

Git Repositories

Testboard GUI Source code and usage instructions for the GUI to control the testboard
Testboard Analysis Scripts for analyzing data taken with testboard, particularly pedestal data and data taken using the onboard pulser

Chip Documentation

The below table contains documentation for most, but not all, of the ASICs on the analog testboard.

Document Description

datasheet_Lauroc1_20190506.pdf

 Documentation for the LAUROC1 pre-amp/shaper. Updated May 6, 2019

COLUTAV2_ds.pdf

 Documentation for the COLUTAv2 ADC. Updated February 2, 2019

lpGBT.pdf

 Documentation for the low power Giga-Bit Transceiver. Updated April 9, 2019

dac9881.pdf

 Documentation for the DAC that provides a voltage to the onboard pulser. Updated September 2016

a10_overview.pdf

a10_datasheet.pdf

 Documentation for the Arria 10 FPGA that controls the ASICs on the board and sends output data to the USB


-- Daniel Williams - 2019-09-26

Comments 


<--/commentPlugin-->

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