C:\Users\Jaro\Documents\NEVIS_65n_ADC\NEVIS_65n_ADC\COLUTA_V3\digital\coluta_slow_control\Source_files/adc_memory.v
C:\Users\Jaro\Documents\NEVIS_65n_ADC\NEVIS_65n_ADC\COLUTA_V3\digital\coluta_slow_control\Source_files/coluta_slow_control.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/CSR_TMR_4.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/CSR_iostate_4.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/i2c_clock_gating_iostate.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/i2c_control.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/i2c_slave_iostate.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/i2c_slave_TMR.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/i2c_synchronizer.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/majority_voter.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/i2c_to_mem_interface.v
../../../Nevis_65n_ADC/Nevis_65n_ADC/COLUTA_V4/digital/coluta_i2c/Source_files/coluta_i2c.v
C:\Users\Jaro\Documents\NEVIS_65n_ADC\NEVIS_65n_ADC\COLUTA_V3\digital\ddpu\Source_files/ddpu.v
C:\Users\Jaro\Documents\NEVIS_65n_ADC\NEVIS_65n_ADC\COLUTA_V3\digital\ddpu\Source_files/ddpu_core.v
C:\Users\Jaro\Documents\NEVIS_65n_ADC\NEVIS_65n_ADC\COLUTA_V3\digital\ddpu\Source_files/serializer_16bit.v
../init_pwr_up_fpga/I2C_master_controller/i2c/i2c/rtl/verilog/timescale.v
../init_pwr_up_fpga/I2C_master_controller/i2c/i2c/rtl/verilog/i2c_master_top.v
../init_pwr_up_fpga/I2C_master_controller/i2c/i2c/rtl/verilog/i2c_master_bit_ctrl.v
../init_pwr_up_fpga/I2C_master_controller/i2c/i2c/rtl/verilog/i2c_master_byte_ctrl.v
../init_pwr_up_fpga/I2C_master_controller/i2c/i2c/rtl/verilog/i2c_master_defines.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/clk_domain_bridge.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/dual_port_memory.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/AD9508.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/ADC121_dp_memory.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/ADC121.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/pll_640MHz.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/adc_rx.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/pll_40MHz.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/in_pll.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/ADC_data_filter.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/pedestal.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/histogram_ram2c.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/hist_bins_ram.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/histogram.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/compare.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/hit_compare.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/AD9650.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/dac.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/histogram.v
C:\Users\Jaro\Documents\FEB2\FEB2_PCB\init_pwr_up_fpga/init_pwr_up_fpga.v
USB_I2C_state_machine.v
FT2232.v
init_feb_power_tester.v
