| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| m7|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1 |
33 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m7|ram_2port_0|altera_syncram_component|auto_generated |
33 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m7|ram_2port_0 |
33 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m7 |
33 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m6|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m6|ram_2port_0|altera_syncram_component|auto_generated |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m6|ram_2port_0 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m6 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m5|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m5|ram_2port_0|altera_syncram_component|auto_generated |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m5|ram_2port_0 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m5 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m4|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m4|ram_2port_0|altera_syncram_component|auto_generated |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m4|ram_2port_0 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m4 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m3|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m3|ram_2port_0|altera_syncram_component|auto_generated |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m3|ram_2port_0 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m3 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m2|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m2|ram_2port_0|altera_syncram_component|auto_generated |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m2|ram_2port_0 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m2 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m1|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m1|ram_2port_0|altera_syncram_component|auto_generated |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m1|ram_2port_0 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m1 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m0|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m0|ram_2port_0|altera_syncram_component|auto_generated |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m0|ram_2port_0 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| m0 |
59 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_msb |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_lsb |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp1_msb |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp_msb |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp_lsb |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp1_msb |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe8 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|ws_dgrp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|rs_dgwp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|fifo_ram |
22 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|wrptr_g1p |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated|rdptr_g1p |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0|dcfifo_component|auto_generated |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|fifo_0 |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0 |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_framealigner_5g12_inst |
9 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_framealigner_10g24_inst |
7 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|t0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].avmm_reset_sync_inst |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|t0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm |
327 |
45 |
0 |
45 |
33 |
45 |
45 |
45 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|t0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs |
510 |
31 |
4 |
31 |
647 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|t0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pma |
201 |
17 |
0 |
17 |
182 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|t0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst |
464 |
0 |
0 |
0 |
398 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|t0|xcvr_native_a10_0|g_xcvr_native_insts[0].twentynm_xcvr_native_inst |
458 |
113 |
0 |
113 |
365 |
113 |
113 |
113 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|t0|xcvr_native_a10_0|alt_xcvr_native_optional_rcfg_logic |
77 |
26 |
38 |
26 |
65 |
26 |
26 |
26 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|t0|xcvr_native_a10_0 |
372 |
234 |
0 |
234 |
135 |
234 |
234 |
234 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|t0 |
138 |
192 |
0 |
192 |
135 |
192 |
192 |
192 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|p1|xcvr_atx_pll_a10_0|a10_xcvr_avmm_inst|avmm_atom_insts[0].avmm_reset_sync_inst |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|p1|xcvr_atx_pll_a10_0|a10_xcvr_avmm_inst |
327 |
279 |
0 |
279 |
33 |
279 |
279 |
279 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|p1|xcvr_atx_pll_a10_0|a10_xcvr_atx_pll_inst |
33 |
19 |
5 |
19 |
46 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|p1|xcvr_atx_pll_a10_0|alt_xcvr_atx_pll_optional_rcfg_logic |
59 |
25 |
27 |
25 |
56 |
25 |
25 |
25 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|p1|xcvr_atx_pll_a10_0 |
104 |
102 |
1 |
102 |
3 |
102 |
102 |
102 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|p1 |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_rx.g_rx[0].g_rx.counter_rx_ready |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_rx.g_rx[0].g_rx.counter_rx_digitalreset |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_rx.g_rx[0].g_rx.counter_rx_analogreset |
4 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_rx.g_rx[0].g_rx.resync_rx_cal_busy |
5 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_tx.g_tx[0].g_tx.counter_tx_ready |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_tx.g_tx[0].g_tx.counter_tx_digitalreset |
4 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_tx.g_tx[0].g_tx.counter_tx_analogreset |
4 |
1 |
0 |
1 |
2 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_tx.g_tx[0].g_tx.g_pll_locked_hyst.counter_pll_locked_hyst |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_tx.g_tx[0].g_tx.resync_tx_cal_busy |
6 |
1 |
0 |
1 |
4 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_pll.counter_pll_powerdown |
4 |
2 |
0 |
2 |
2 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0|g_reset_sync.alt_xcvr_resync_reset |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0|xcvr_reset_control_0 |
12 |
5 |
1 |
5 |
7 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst|r0 |
7 |
1 |
0 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| f0|mgt_inst |
45 |
0 |
8 |
0 |
38 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDescramlber_inst|\fec12_gen:descrambler53bitOrder49_h1_inst |
57 |
0 |
0 |
0 |
53 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDescramlber_inst|\fec12_gen:descrambler51bitOrder49_h0_inst |
55 |
0 |
0 |
0 |
51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDescramlber_inst|\fec12_gen:descrambler51bitOrder49_l1_inst |
55 |
0 |
0 |
0 |
51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDescramlber_inst|\fec12_gen:descrambler51bitOrder49_l0_inst |
55 |
0 |
0 |
0 |
51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDescramlber_inst|\fec5_gen:descrambler60bitOrder58_h1_inst |
64 |
0 |
0 |
0 |
60 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDescramlber_inst|\fec5_gen:descrambler58bitOrder58_h0_inst |
62 |
0 |
0 |
0 |
58 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDescramlber_inst|\fec5_gen:descrambler58bitOrder58_l1_inst |
62 |
0 |
0 |
0 |
58 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDescramlber_inst|\fec5_gen:descrambler58bitOrder58_l0_inst |
62 |
0 |
0 |
0 |
58 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDescramlber_inst |
444 |
0 |
0 |
0 |
440 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDecoder_inst|\fec12_dec_gen:dec10g24_fec12_gen:rs_decoder_N15K13_c5_inst |
60 |
40 |
0 |
40 |
52 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDecoder_inst|\fec12_dec_gen:dec10g24_fec12_gen:rs_decoder_N15K13_c4_inst |
60 |
36 |
0 |
36 |
52 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDecoder_inst|\fec12_dec_gen:dec10g24_fec12_gen:rs_decoder_N15K13_c3_inst |
60 |
32 |
0 |
32 |
52 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDecoder_inst|\fec12_dec_gen:rs_decoder_N15K13_c2_inst |
60 |
32 |
0 |
32 |
52 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDecoder_inst|\fec12_dec_gen:rs_decoder_N15K13_c1_inst |
60 |
32 |
0 |
32 |
52 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDecoder_inst|\fec12_dec_gen:rs_decoder_N15K13_c0_inst |
60 |
32 |
0 |
32 |
52 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDecoder_inst|\fec5_dec_gen:dec10g24_fec5_gen:rs_decoder_N31K29_c1_inst |
155 |
58 |
0 |
58 |
145 |
58 |
58 |
58 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDecoder_inst|\fec5_dec_gen:rs_decoder_N31K29_c0_inst |
155 |
52 |
0 |
52 |
145 |
52 |
52 |
52 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDecoder_inst |
510 |
0 |
0 |
0 |
440 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDeinterleaver_inst|\fec12_gen:upLinkDeinterleaver_fec12_inst |
258 |
0 |
2 |
0 |
254 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDeinterleaver_inst|\fec5_gen:upLinkDeinterleaver_fec5_inst |
258 |
0 |
2 |
0 |
254 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst|upLinkDeinterleaver_inst |
258 |
0 |
0 |
0 |
508 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_Uplink_datapath_inst |
264 |
0 |
0 |
0 |
236 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|rxGearbox_5g12_inst |
35 |
0 |
0 |
0 |
258 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|rxGearbox_10g24_inst |
35 |
0 |
0 |
0 |
258 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|txGearbox_inst |
68 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_dataPath_inst|downLinkInterleaver_inst |
61 |
4 |
0 |
4 |
64 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_dataPath_inst|downLinkFECEncoder_inst|RSE3_inst |
15 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_dataPath_inst|downLinkFECEncoder_inst|RSE2_inst |
15 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_dataPath_inst|downLinkFECEncoder_inst|RSE1_inst |
15 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_dataPath_inst|downLinkFECEncoder_inst|RSE0_inst |
15 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_dataPath_inst|downLinkFECEncoder_inst |
37 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_dataPath_inst|scrambler36bitOrder36_inst |
40 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0|LpGBT_FPGA_dataPath_inst |
42 |
0 |
0 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f0 |
382 |
338 |
2 |
338 |
242 |
338 |
338 |
338 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_msb |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_lsb |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp1_msb |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp_msb |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp_lsb |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp1_msb |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb |
10 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe8 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|ws_dgrp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe8 |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|rs_dgwp |
10 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|fifo_ram |
57 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|wrptr_g1p |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated|rdptr_g1p |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0|dcfifo_component|auto_generated |
40 |
0 |
0 |
0 |
38 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36|fifo_0 |
40 |
0 |
0 |
0 |
38 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f36 |
40 |
1 |
0 |
1 |
36 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| ldpm1|m1|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1 |
63 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ldpm1|m1|ram_2port_0|altera_syncram_component|auto_generated |
63 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ldpm1|m1|ram_2port_0 |
63 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ldpm1|m1 |
63 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ldpm1 |
283 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| lc1 |
59 |
0 |
7 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| BC_1 |
19 |
0 |
2 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| pa1 |
284 |
0 |
2 |
0 |
282 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C|byte_controller|bit_controller |
27 |
2 |
0 |
2 |
8 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| I2C|byte_controller |
35 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C |
19 |
1 |
0 |
1 |
13 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| usb_i2c_sm |
268 |
0 |
0 |
0 |
272 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| dac1 |
36 |
0 |
6 |
0 |
28 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|rdemp_eq_comp_msb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|rdemp_eq_comp_lsb_mux |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_msb |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp1_msb |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|wrfull_eq_comp1_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp_msb |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp1_msb |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|rdempty_eq_comp1_lsb |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|ws_dgrp|dffpipe6 |
6 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|ws_dgrp |
6 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 |
6 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|rs_dgwp |
6 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|fifo_ram |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|wrptr_g1p |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated|rdptr_g1p |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0|dcfifo_component|auto_generated |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1|fifo_0 |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| f1 |
10 |
1 |
0 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| p0|iopll_0 |
2 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p0 |
2 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |