// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition"

// DATE "05/17/2019 13:19:17"

// 
// Device: Altera 10AX016E3F27E1HG Package FBGA672
// 

// 
// This greybox netlist file is for third party Synthesis Tools
// for timing and resource estimation only.
// 


module fifo_clk_bridge (
	data,
	wrreq,
	rdreq,
	wrclk,
	rdclk,
	q,
	rdempty,
	wrfull)/* synthesis synthesis_greybox=0 */;
input 	[5:0] data;
input 	wrreq;
input 	rdreq;
input 	wrclk;
input 	rdclk;
output 	[5:0] q;
output 	rdempty;
output 	wrfull;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[0] ;
wire \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[1] ;
wire \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[2] ;
wire \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[3] ;
wire \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[4] ;
wire \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[5] ;
wire \fifo_0|dcfifo_component|auto_generated|int_rdempty~combout ;
wire \fifo_0|dcfifo_component|auto_generated|int_wrfull~combout ;
wire \wrreq~input_o ;
wire \rdreq~input_o ;
wire \wrclk~input_o ;
wire \rdclk~input_o ;
wire \data[0]~input_o ;
wire \data[1]~input_o ;
wire \data[2]~input_o ;
wire \data[3]~input_o ;
wire \data[4]~input_o ;
wire \data[5]~input_o ;


fifo_clk_bridge_fifo_clk_bridge_fifo_181_xtqoudq fifo_0(
	.q_b_0(\fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[0] ),
	.q_b_1(\fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[1] ),
	.q_b_2(\fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[2] ),
	.q_b_3(\fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[3] ),
	.q_b_4(\fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[4] ),
	.q_b_5(\fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[5] ),
	.int_rdempty(\fifo_0|dcfifo_component|auto_generated|int_rdempty~combout ),
	.int_wrfull(\fifo_0|dcfifo_component|auto_generated|int_wrfull~combout ),
	.wrreq(\wrreq~input_o ),
	.rdreq(\rdreq~input_o ),
	.wrclk(\wrclk~input_o ),
	.rdclk(\rdclk~input_o ),
	.data_0(\data[0]~input_o ),
	.data_1(\data[1]~input_o ),
	.data_2(\data[2]~input_o ),
	.data_3(\data[3]~input_o ),
	.data_4(\data[4]~input_o ),
	.data_5(\data[5]~input_o ));

assign \wrreq~input_o  = wrreq;

assign \rdreq~input_o  = rdreq;

assign \wrclk~input_o  = wrclk;

assign \rdclk~input_o  = rdclk;

assign \data[0]~input_o  = data[0];

assign \data[1]~input_o  = data[1];

assign \data[2]~input_o  = data[2];

assign \data[3]~input_o  = data[3];

assign \data[4]~input_o  = data[4];

assign \data[5]~input_o  = data[5];

assign q[0] = \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[0] ;

assign q[1] = \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[1] ;

assign q[2] = \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[2] ;

assign q[3] = \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[3] ;

assign q[4] = \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[4] ;

assign q[5] = \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[5] ;

assign rdempty = \fifo_0|dcfifo_component|auto_generated|int_rdempty~combout ;

assign wrfull = \fifo_0|dcfifo_component|auto_generated|int_wrfull~combout ;

endmodule

module fifo_clk_bridge_fifo_clk_bridge_fifo_181_xtqoudq (
	q_b_0,
	q_b_1,
	q_b_2,
	q_b_3,
	q_b_4,
	q_b_5,
	int_rdempty,
	int_wrfull,
	wrreq,
	rdreq,
	wrclk,
	rdclk,
	data_0,
	data_1,
	data_2,
	data_3,
	data_4,
	data_5)/* synthesis synthesis_greybox=0 */;
output 	q_b_0;
output 	q_b_1;
output 	q_b_2;
output 	q_b_3;
output 	q_b_4;
output 	q_b_5;
output 	int_rdempty;
output 	int_wrfull;
input 	wrreq;
input 	rdreq;
input 	wrclk;
input 	rdclk;
input 	data_0;
input 	data_1;
input 	data_2;
input 	data_3;
input 	data_4;
input 	data_5;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



fifo_clk_bridge_dcfifo_1 dcfifo_component(
	.q({q_b_5,q_b_4,q_b_3,q_b_2,q_b_1,q_b_0}),
	.int_rdempty(int_rdempty),
	.int_wrfull(int_wrfull),
	.wrreq(wrreq),
	.rdreq(rdreq),
	.wrclk(wrclk),
	.rdclk(rdclk),
	.data({data_5,data_4,data_3,data_2,data_1,data_0}));

endmodule

module fifo_clk_bridge_dcfifo_1 (
	q,
	int_rdempty,
	int_wrfull,
	wrreq,
	rdreq,
	wrclk,
	rdclk,
	data)/* synthesis synthesis_greybox=0 */;
output 	[5:0] q;
output 	int_rdempty;
output 	int_wrfull;
input 	wrreq;
input 	rdreq;
input 	wrclk;
input 	rdclk;
input 	[5:0] data;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



fifo_clk_bridge_dcfifo_9312 auto_generated(
	.q({q[5],q[4],q[3],q[2],q[1],q[0]}),
	.int_rdempty1(int_rdempty),
	.int_wrfull1(int_wrfull),
	.wrreq(wrreq),
	.rdreq(rdreq),
	.wrclk(wrclk),
	.rdclk(rdclk),
	.data({data[5],data[4],data[3],data[2],data[1],data[0]}));

endmodule

module fifo_clk_bridge_dcfifo_9312 (
	q,
	int_rdempty1,
	int_wrfull1,
	wrreq,
	rdreq,
	wrclk,
	rdclk,
	data)/* synthesis synthesis_greybox=0 */;
output 	[5:0] q;
output 	int_rdempty1;
output 	int_wrfull1;
input 	wrreq;
input 	rdreq;
input 	wrclk;
input 	rdclk;
input 	[5:0] data;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \valid_wrreq~0_combout ;
wire \valid_rdreq~0_combout ;
wire \wrptr_g[0]~q ;
wire \wrptr_g[1]~q ;
wire \wrptr_g[2]~q ;
wire \wrptr_g[4]~q ;
wire \wrptr_g[3]~q ;
wire \ram_address_a[3]~combout ;
wire \rdptr_g1p|counter1a0~q ;
wire \rdptr_g1p|counter1a1~q ;
wire \rdptr_g1p|counter1a2~q ;
wire \rdptr_g1p|counter1a3~q ;
wire \rdptr_g1p|counter1a4~q ;
wire \rdptr_g1p|_~0_combout ;
wire \rs_dgwp|dffpipe6|dffe8a[1]~q ;
wire \rdptr_g[1]~q ;
wire \rs_dgwp|dffpipe6|dffe8a[2]~q ;
wire \rs_dgwp|dffpipe6|dffe8a[0]~q ;
wire \rdptr_g[2]~q ;
wire \rdptr_g[0]~q ;
wire \rdemp_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~2_combout ;
wire \rdptr_g[3]~q ;
wire \rs_dgwp|dffpipe6|dffe8a[3]~q ;
wire \rdptr_g[4]~q ;
wire \rs_dgwp|dffpipe6|dffe8a[4]~q ;
wire \rdemp_eq_comp_msb_mux|l1_w0_n0_mux_dataout~0_combout ;
wire \ws_dgrp|dffpipe6|dffe8a[1]~q ;
wire \wrptr_g1p|counter3a2~q ;
wire \ws_dgrp|dffpipe6|dffe8a[2]~q ;
wire \wrptr_g1p|counter3a0~q ;
wire \ws_dgrp|dffpipe6|dffe8a[0]~q ;
wire \wrptr_g1p|counter3a1~q ;
wire \wrfull_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~2_combout ;
wire \wrptr_g1p|counter3a3~q ;
wire \ws_dgrp|dffpipe6|dffe8a[3]~q ;
wire \wrptr_g1p|counter3a4~q ;
wire \ws_dgrp|dffpipe6|dffe8a[4]~q ;
wire \wrfull_eq_comp_msb_mux|l1_w0_n0_mux_dataout~2_combout ;
wire \delayed_wrptr_g[1]~q ;
wire \delayed_wrptr_g[2]~q ;
wire \delayed_wrptr_g[0]~q ;
wire \delayed_wrptr_g[3]~q ;
wire \delayed_wrptr_g[4]~q ;
wire \wrptr_g[0]~0_combout ;
wire \rdptr_g[0]~0_combout ;
wire \rdptr_g1p|counter1a0~_wirecell_combout ;
wire \rdemp_eq_comp_lsb_aeb~q ;
wire \rdemp_eq_comp_msb_aeb~q ;
wire \wrfull_eq_comp_lsb_mux_reg~q ;
wire \wrfull_eq_comp_msb_mux_reg~q ;


fifo_clk_bridge_altsyncram_l7a1 fifo_ram(
	.q_b({q[5],q[4],q[3],q[2],q[1],q[0]}),
	.wren_a(\valid_wrreq~0_combout ),
	.addressstall_b(\valid_rdreq~0_combout ),
	.clocken1(\valid_rdreq~0_combout ),
	.address_a({\ram_address_a[3]~combout ,\wrptr_g[2]~q ,\wrptr_g[1]~q ,\wrptr_g[0]~q }),
	.address_b({\rdptr_g1p|_~0_combout ,\rdptr_g1p|counter1a2~q ,\rdptr_g1p|counter1a1~q ,\rdptr_g1p|counter1a0~_wirecell_combout }),
	.clock0(wrclk),
	.clock1(rdclk),
	.data_a({data[5],data[4],data[3],data[2],data[1],data[0]}));

fifo_clk_bridge_a_graycounter_imb wrptr_g1p(
	.wrfull_eq_comp_lsb_mux_reg(\wrfull_eq_comp_lsb_mux_reg~q ),
	.wrfull_eq_comp_msb_mux_reg(\wrfull_eq_comp_msb_mux_reg~q ),
	.int_wrfull(int_wrfull1),
	.valid_wrreq(\valid_wrreq~0_combout ),
	.counter3a21(\wrptr_g1p|counter3a2~q ),
	.counter3a01(\wrptr_g1p|counter3a0~q ),
	.counter3a11(\wrptr_g1p|counter3a1~q ),
	.counter3a31(\wrptr_g1p|counter3a3~q ),
	.counter3a41(\wrptr_g1p|counter3a4~q ),
	.wrreq(wrreq),
	.clock(wrclk));

fifo_clk_bridge_a_graycounter_m86 rdptr_g1p(
	.rdemp_eq_comp_lsb_aeb(\rdemp_eq_comp_lsb_aeb~q ),
	.rdemp_eq_comp_msb_aeb(\rdemp_eq_comp_msb_aeb~q ),
	.int_rdempty(int_rdempty1),
	.valid_rdreq(\valid_rdreq~0_combout ),
	.counter1a01(\rdptr_g1p|counter1a0~q ),
	.counter1a11(\rdptr_g1p|counter1a1~q ),
	.counter1a21(\rdptr_g1p|counter1a2~q ),
	.counter1a31(\rdptr_g1p|counter1a3~q ),
	.counter1a41(\rdptr_g1p|counter1a4~q ),
	._(\rdptr_g1p|_~0_combout ),
	.counter1a02(\rdptr_g1p|counter1a0~_wirecell_combout ),
	.rdreq(rdreq),
	.clock(rdclk));

fifo_clk_bridge_mux_ij7 rdemp_eq_comp_lsb_mux(
	.int_rdempty(int_rdempty1),
	.counter1a0(\rdptr_g1p|counter1a0~q ),
	.counter1a1(\rdptr_g1p|counter1a1~q ),
	.counter1a2(\rdptr_g1p|counter1a2~q ),
	.dffe8a_1(\rs_dgwp|dffpipe6|dffe8a[1]~q ),
	.rdptr_g_1(\rdptr_g[1]~q ),
	.dffe8a_2(\rs_dgwp|dffpipe6|dffe8a[2]~q ),
	.dffe8a_0(\rs_dgwp|dffpipe6|dffe8a[0]~q ),
	.rdptr_g_2(\rdptr_g[2]~q ),
	.rdptr_g_0(\rdptr_g[0]~q ),
	.l1_w0_n0_mux_dataout(\rdemp_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.rdreq(rdreq));

fifo_clk_bridge_alt_synch_pipe_d9l_1 ws_dgrp(
	.rdptr_g_1(\rdptr_g[1]~q ),
	.rdptr_g_2(\rdptr_g[2]~q ),
	.rdptr_g_0(\rdptr_g[0]~q ),
	.rdptr_g_3(\rdptr_g[3]~q ),
	.rdptr_g_4(\rdptr_g[4]~q ),
	.dffe8a_1(\ws_dgrp|dffpipe6|dffe8a[1]~q ),
	.dffe8a_2(\ws_dgrp|dffpipe6|dffe8a[2]~q ),
	.dffe8a_0(\ws_dgrp|dffpipe6|dffe8a[0]~q ),
	.dffe8a_3(\ws_dgrp|dffpipe6|dffe8a[3]~q ),
	.dffe8a_4(\ws_dgrp|dffpipe6|dffe8a[4]~q ),
	.clock(wrclk));

fifo_clk_bridge_alt_synch_pipe_d9l rs_dgwp(
	.dffe8a_1(\rs_dgwp|dffpipe6|dffe8a[1]~q ),
	.dffe8a_2(\rs_dgwp|dffpipe6|dffe8a[2]~q ),
	.dffe8a_0(\rs_dgwp|dffpipe6|dffe8a[0]~q ),
	.dffe8a_3(\rs_dgwp|dffpipe6|dffe8a[3]~q ),
	.dffe8a_4(\rs_dgwp|dffpipe6|dffe8a[4]~q ),
	.delayed_wrptr_g_1(\delayed_wrptr_g[1]~q ),
	.delayed_wrptr_g_2(\delayed_wrptr_g[2]~q ),
	.delayed_wrptr_g_0(\delayed_wrptr_g[0]~q ),
	.delayed_wrptr_g_3(\delayed_wrptr_g[3]~q ),
	.delayed_wrptr_g_4(\delayed_wrptr_g[4]~q ),
	.clock(rdclk));

fifo_clk_bridge_mux_ij7_3 wrfull_eq_comp_msb_mux(
	.int_wrfull(int_wrfull1),
	.wrptr_g_4(\wrptr_g[4]~q ),
	.wrptr_g_3(\wrptr_g[3]~q ),
	.counter3a3(\wrptr_g1p|counter3a3~q ),
	.dffe8a_3(\ws_dgrp|dffpipe6|dffe8a[3]~q ),
	.counter3a4(\wrptr_g1p|counter3a4~q ),
	.dffe8a_4(\ws_dgrp|dffpipe6|dffe8a[4]~q ),
	.l1_w0_n0_mux_dataout(\wrfull_eq_comp_msb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.wrreq(wrreq));

fifo_clk_bridge_mux_ij7_2 wrfull_eq_comp_lsb_mux(
	.int_wrfull(int_wrfull1),
	.wrptr_g_0(\wrptr_g[0]~q ),
	.wrptr_g_1(\wrptr_g[1]~q ),
	.wrptr_g_2(\wrptr_g[2]~q ),
	.dffe8a_1(\ws_dgrp|dffpipe6|dffe8a[1]~q ),
	.counter3a2(\wrptr_g1p|counter3a2~q ),
	.dffe8a_2(\ws_dgrp|dffpipe6|dffe8a[2]~q ),
	.counter3a0(\wrptr_g1p|counter3a0~q ),
	.dffe8a_0(\ws_dgrp|dffpipe6|dffe8a[0]~q ),
	.counter3a1(\wrptr_g1p|counter3a1~q ),
	.l1_w0_n0_mux_dataout(\wrfull_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.wrreq(wrreq));

fifo_clk_bridge_mux_ij7_1 rdemp_eq_comp_msb_mux(
	.rdemp_eq_comp_lsb_aeb(\rdemp_eq_comp_lsb_aeb~q ),
	.rdemp_eq_comp_msb_aeb(\rdemp_eq_comp_msb_aeb~q ),
	.counter1a3(\rdptr_g1p|counter1a3~q ),
	.counter1a4(\rdptr_g1p|counter1a4~q ),
	.rdptr_g_3(\rdptr_g[3]~q ),
	.dffe8a_3(\rs_dgwp|dffpipe6|dffe8a[3]~q ),
	.rdptr_g_4(\rdptr_g[4]~q ),
	.dffe8a_4(\rs_dgwp|dffpipe6|dffe8a[4]~q ),
	.l1_w0_n0_mux_dataout(\rdemp_eq_comp_msb_mux|l1_w0_n0_mux_dataout~0_combout ),
	.rdreq(rdreq));

twentynm_lcell_comb \valid_wrreq~0 (
	.dataa(!\wrfull_eq_comp_lsb_mux_reg~q ),
	.datab(!\wrfull_eq_comp_msb_mux_reg~q ),
	.datac(!wrreq),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\valid_wrreq~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \valid_wrreq~0 .extended_lut = "off";
defparam \valid_wrreq~0 .lut_mask = 64'h0E0E0E0E0E0E0E0E;
defparam \valid_wrreq~0 .shared_arith = "off";

twentynm_lcell_comb \valid_rdreq~0 (
	.dataa(!\rdemp_eq_comp_lsb_aeb~q ),
	.datab(!\rdemp_eq_comp_msb_aeb~q ),
	.datac(!rdreq),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\valid_rdreq~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \valid_rdreq~0 .extended_lut = "off";
defparam \valid_rdreq~0 .lut_mask = 64'h0707070707070707;
defparam \valid_rdreq~0 .shared_arith = "off";

dffeas \wrptr_g[0] (
	.clk(wrclk),
	.d(\wrptr_g[0]~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[0]~q ),
	.prn(vcc));
defparam \wrptr_g[0] .is_wysiwyg = "true";
defparam \wrptr_g[0] .power_up = "low";

dffeas \wrptr_g[1] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter3a1~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[1]~q ),
	.prn(vcc));
defparam \wrptr_g[1] .is_wysiwyg = "true";
defparam \wrptr_g[1] .power_up = "low";

dffeas \wrptr_g[2] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter3a2~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[2]~q ),
	.prn(vcc));
defparam \wrptr_g[2] .is_wysiwyg = "true";
defparam \wrptr_g[2] .power_up = "low";

dffeas \wrptr_g[4] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter3a4~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[4]~q ),
	.prn(vcc));
defparam \wrptr_g[4] .is_wysiwyg = "true";
defparam \wrptr_g[4] .power_up = "low";

dffeas \wrptr_g[3] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter3a3~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[3]~q ),
	.prn(vcc));
defparam \wrptr_g[3] .is_wysiwyg = "true";
defparam \wrptr_g[3] .power_up = "low";

twentynm_lcell_comb \ram_address_a[3] (
	.dataa(!\wrptr_g[4]~q ),
	.datab(!\wrptr_g[3]~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ram_address_a[3]~combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \ram_address_a[3] .extended_lut = "off";
defparam \ram_address_a[3] .lut_mask = 64'h6666666666666666;
defparam \ram_address_a[3] .shared_arith = "off";

dffeas \rdptr_g[1] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a1~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[1]~q ),
	.prn(vcc));
defparam \rdptr_g[1] .is_wysiwyg = "true";
defparam \rdptr_g[1] .power_up = "low";

dffeas \rdptr_g[2] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a2~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[2]~q ),
	.prn(vcc));
defparam \rdptr_g[2] .is_wysiwyg = "true";
defparam \rdptr_g[2] .power_up = "low";

dffeas \rdptr_g[0] (
	.clk(rdclk),
	.d(\rdptr_g[0]~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[0]~q ),
	.prn(vcc));
defparam \rdptr_g[0] .is_wysiwyg = "true";
defparam \rdptr_g[0] .power_up = "low";

dffeas \rdptr_g[3] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a3~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[3]~q ),
	.prn(vcc));
defparam \rdptr_g[3] .is_wysiwyg = "true";
defparam \rdptr_g[3] .power_up = "low";

dffeas \rdptr_g[4] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a4~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[4]~q ),
	.prn(vcc));
defparam \rdptr_g[4] .is_wysiwyg = "true";
defparam \rdptr_g[4] .power_up = "low";

dffeas \delayed_wrptr_g[1] (
	.clk(wrclk),
	.d(\wrptr_g[1]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[1]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[1] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[1] .power_up = "low";

dffeas \delayed_wrptr_g[2] (
	.clk(wrclk),
	.d(\wrptr_g[2]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[2]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[2] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[2] .power_up = "low";

dffeas \delayed_wrptr_g[0] (
	.clk(wrclk),
	.d(\wrptr_g[0]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[0]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[0] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[0] .power_up = "low";

dffeas \delayed_wrptr_g[3] (
	.clk(wrclk),
	.d(\wrptr_g[3]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[3]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[3] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[3] .power_up = "low";

dffeas \delayed_wrptr_g[4] (
	.clk(wrclk),
	.d(\wrptr_g[4]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[4]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[4] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[4] .power_up = "low";

twentynm_lcell_comb \wrptr_g[0]~0 (
	.dataa(!\wrptr_g1p|counter3a0~q ),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\wrptr_g[0]~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \wrptr_g[0]~0 .extended_lut = "off";
defparam \wrptr_g[0]~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \wrptr_g[0]~0 .shared_arith = "off";

twentynm_lcell_comb \rdptr_g[0]~0 (
	.dataa(!\rdptr_g1p|counter1a0~q ),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rdptr_g[0]~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \rdptr_g[0]~0 .extended_lut = "off";
defparam \rdptr_g[0]~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \rdptr_g[0]~0 .shared_arith = "off";

twentynm_lcell_comb int_rdempty(
	.dataa(!\rdemp_eq_comp_lsb_aeb~q ),
	.datab(!\rdemp_eq_comp_msb_aeb~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(int_rdempty1),
	.sumout(),
	.cout(),
	.shareout());
defparam int_rdempty.extended_lut = "off";
defparam int_rdempty.lut_mask = 64'h8888888888888888;
defparam int_rdempty.shared_arith = "off";

twentynm_lcell_comb int_wrfull(
	.dataa(!\wrfull_eq_comp_lsb_mux_reg~q ),
	.datab(!\wrfull_eq_comp_msb_mux_reg~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(int_wrfull1),
	.sumout(),
	.cout(),
	.shareout());
defparam int_wrfull.extended_lut = "off";
defparam int_wrfull.lut_mask = 64'h1111111111111111;
defparam int_wrfull.shared_arith = "off";

dffeas rdemp_eq_comp_lsb_aeb(
	.clk(rdclk),
	.d(\rdemp_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\rdemp_eq_comp_lsb_aeb~q ),
	.prn(vcc));
defparam rdemp_eq_comp_lsb_aeb.is_wysiwyg = "true";
defparam rdemp_eq_comp_lsb_aeb.power_up = "low";

dffeas rdemp_eq_comp_msb_aeb(
	.clk(rdclk),
	.d(\rdemp_eq_comp_msb_mux|l1_w0_n0_mux_dataout~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\rdemp_eq_comp_msb_aeb~q ),
	.prn(vcc));
defparam rdemp_eq_comp_msb_aeb.is_wysiwyg = "true";
defparam rdemp_eq_comp_msb_aeb.power_up = "low";

dffeas wrfull_eq_comp_lsb_mux_reg(
	.clk(wrclk),
	.d(\wrfull_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\wrfull_eq_comp_lsb_mux_reg~q ),
	.prn(vcc));
defparam wrfull_eq_comp_lsb_mux_reg.is_wysiwyg = "true";
defparam wrfull_eq_comp_lsb_mux_reg.power_up = "low";

dffeas wrfull_eq_comp_msb_mux_reg(
	.clk(wrclk),
	.d(\wrfull_eq_comp_msb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\wrfull_eq_comp_msb_mux_reg~q ),
	.prn(vcc));
defparam wrfull_eq_comp_msb_mux_reg.is_wysiwyg = "true";
defparam wrfull_eq_comp_msb_mux_reg.power_up = "low";

endmodule

module fifo_clk_bridge_a_graycounter_imb (
	wrfull_eq_comp_lsb_mux_reg,
	wrfull_eq_comp_msb_mux_reg,
	int_wrfull,
	valid_wrreq,
	counter3a21,
	counter3a01,
	counter3a11,
	counter3a31,
	counter3a41,
	wrreq,
	clock)/* synthesis synthesis_greybox=0 */;
input 	wrfull_eq_comp_lsb_mux_reg;
input 	wrfull_eq_comp_msb_mux_reg;
input 	int_wrfull;
input 	valid_wrreq;
output 	counter3a21;
output 	counter3a01;
output 	counter3a11;
output 	counter3a31;
output 	counter3a41;
input 	wrreq;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \_~0_combout ;
wire \parity4~q ;
wire \counter3a2~0_combout ;
wire \counter3a0~0_combout ;
wire \counter3a1~0_combout ;
wire \counter3a3~0_combout ;
wire \counter3a4~0_combout ;


dffeas counter3a2(
	.clk(clock),
	.d(\counter3a2~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter3a21),
	.prn(vcc));
defparam counter3a2.is_wysiwyg = "true";
defparam counter3a2.power_up = "low";

dffeas counter3a0(
	.clk(clock),
	.d(\counter3a0~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter3a01),
	.prn(vcc));
defparam counter3a0.is_wysiwyg = "true";
defparam counter3a0.power_up = "low";

dffeas counter3a1(
	.clk(clock),
	.d(\counter3a1~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter3a11),
	.prn(vcc));
defparam counter3a1.is_wysiwyg = "true";
defparam counter3a1.power_up = "low";

dffeas counter3a3(
	.clk(clock),
	.d(\counter3a3~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter3a31),
	.prn(vcc));
defparam counter3a3.is_wysiwyg = "true";
defparam counter3a3.power_up = "low";

dffeas counter3a4(
	.clk(clock),
	.d(\counter3a4~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter3a41),
	.prn(vcc));
defparam counter3a4.is_wysiwyg = "true";
defparam counter3a4.power_up = "low";

twentynm_lcell_comb \_~0 (
	.dataa(!counter3a21),
	.datab(!counter3a01),
	.datac(!counter3a11),
	.datad(!counter3a31),
	.datae(!counter3a41),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~0 .extended_lut = "off";
defparam \_~0 .lut_mask = 64'h9669699696696996;
defparam \_~0 .shared_arith = "off";

dffeas parity4(
	.clk(clock),
	.d(\_~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_wrreq),
	.q(\parity4~q ),
	.prn(vcc));
defparam parity4.is_wysiwyg = "true";
defparam parity4.power_up = "low";

twentynm_lcell_comb \counter3a2~0 (
	.dataa(!int_wrfull),
	.datab(!wrreq),
	.datac(!counter3a21),
	.datad(!counter3a01),
	.datae(!counter3a11),
	.dataf(!\parity4~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter3a2~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter3a2~0 .extended_lut = "off";
defparam \counter3a2~0 .lut_mask = 64'h0F0F0F2D0F0F0F0F;
defparam \counter3a2~0 .shared_arith = "off";

twentynm_lcell_comb \counter3a0~0 (
	.dataa(!wrfull_eq_comp_lsb_mux_reg),
	.datab(!wrfull_eq_comp_msb_mux_reg),
	.datac(!wrreq),
	.datad(!counter3a01),
	.datae(!\parity4~q ),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter3a0~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter3a0~0 .extended_lut = "off";
defparam \counter3a0~0 .lut_mask = 64'h00FF0EF100FF0EF1;
defparam \counter3a0~0 .shared_arith = "off";

twentynm_lcell_comb \counter3a1~0 (
	.dataa(!wrfull_eq_comp_lsb_mux_reg),
	.datab(!wrfull_eq_comp_msb_mux_reg),
	.datac(!wrreq),
	.datad(!counter3a01),
	.datae(!counter3a11),
	.dataf(!\parity4~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter3a1~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter3a1~0 .extended_lut = "off";
defparam \counter3a1~0 .lut_mask = 64'h0E00F1FF0000FFFF;
defparam \counter3a1~0 .shared_arith = "off";

twentynm_lcell_comb \counter3a3~0 (
	.dataa(!valid_wrreq),
	.datab(!counter3a21),
	.datac(!counter3a01),
	.datad(!counter3a11),
	.datae(!counter3a31),
	.dataf(!\parity4~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter3a3~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter3a3~0 .extended_lut = "off";
defparam \counter3a3~0 .lut_mask = 64'h0100FEFF0000FFFF;
defparam \counter3a3~0 .shared_arith = "off";

twentynm_lcell_comb \counter3a4~0 (
	.dataa(!valid_wrreq),
	.datab(!counter3a21),
	.datac(!counter3a01),
	.datad(!counter3a11),
	.datae(!counter3a41),
	.dataf(!\parity4~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter3a4~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter3a4~0 .extended_lut = "off";
defparam \counter3a4~0 .lut_mask = 64'h0400FBFF0000FFFF;
defparam \counter3a4~0 .shared_arith = "off";

endmodule

module fifo_clk_bridge_a_graycounter_m86 (
	rdemp_eq_comp_lsb_aeb,
	rdemp_eq_comp_msb_aeb,
	int_rdempty,
	valid_rdreq,
	counter1a01,
	counter1a11,
	counter1a21,
	counter1a31,
	counter1a41,
	_,
	counter1a02,
	rdreq,
	clock)/* synthesis synthesis_greybox=0 */;
input 	rdemp_eq_comp_lsb_aeb;
input 	rdemp_eq_comp_msb_aeb;
input 	int_rdempty;
input 	valid_rdreq;
output 	counter1a01;
output 	counter1a11;
output 	counter1a21;
output 	counter1a31;
output 	counter1a41;
output 	_;
output 	counter1a02;
input 	rdreq;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \_~1_combout ;
wire \parity2~q ;
wire \counter1a0~0_combout ;
wire \counter1a1~0_combout ;
wire \counter1a2~0_combout ;
wire \counter1a3~0_combout ;
wire \counter1a4~0_combout ;


dffeas counter1a0(
	.clk(clock),
	.d(\counter1a0~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a01),
	.prn(vcc));
defparam counter1a0.is_wysiwyg = "true";
defparam counter1a0.power_up = "low";

dffeas counter1a1(
	.clk(clock),
	.d(\counter1a1~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a11),
	.prn(vcc));
defparam counter1a1.is_wysiwyg = "true";
defparam counter1a1.power_up = "low";

dffeas counter1a2(
	.clk(clock),
	.d(\counter1a2~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a21),
	.prn(vcc));
defparam counter1a2.is_wysiwyg = "true";
defparam counter1a2.power_up = "low";

dffeas counter1a3(
	.clk(clock),
	.d(\counter1a3~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a31),
	.prn(vcc));
defparam counter1a3.is_wysiwyg = "true";
defparam counter1a3.power_up = "low";

dffeas counter1a4(
	.clk(clock),
	.d(\counter1a4~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a41),
	.prn(vcc));
defparam counter1a4.is_wysiwyg = "true";
defparam counter1a4.power_up = "low";

twentynm_lcell_comb \_~0 (
	.dataa(!counter1a31),
	.datab(!counter1a41),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(_),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~0 .extended_lut = "off";
defparam \_~0 .lut_mask = 64'h6666666666666666;
defparam \_~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a0~_wirecell (
	.dataa(!counter1a01),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(counter1a02),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a0~_wirecell .extended_lut = "off";
defparam \counter1a0~_wirecell .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \counter1a0~_wirecell .shared_arith = "off";

twentynm_lcell_comb \_~1 (
	.dataa(!counter1a01),
	.datab(!counter1a11),
	.datac(!counter1a21),
	.datad(!counter1a31),
	.datae(!counter1a41),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~1 .extended_lut = "off";
defparam \_~1 .lut_mask = 64'h9669699696696996;
defparam \_~1 .shared_arith = "off";

dffeas parity2(
	.clk(clock),
	.d(\_~1_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_rdreq),
	.q(\parity2~q ),
	.prn(vcc));
defparam parity2.is_wysiwyg = "true";
defparam parity2.power_up = "low";

twentynm_lcell_comb \counter1a0~0 (
	.dataa(!rdemp_eq_comp_lsb_aeb),
	.datab(!rdemp_eq_comp_msb_aeb),
	.datac(!rdreq),
	.datad(!counter1a01),
	.datae(!\parity2~q ),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a0~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a0~0 .extended_lut = "off";
defparam \counter1a0~0 .lut_mask = 64'h00FF07F800FF07F8;
defparam \counter1a0~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a1~0 (
	.dataa(!rdemp_eq_comp_lsb_aeb),
	.datab(!rdemp_eq_comp_msb_aeb),
	.datac(!rdreq),
	.datad(!counter1a01),
	.datae(!counter1a11),
	.dataf(!\parity2~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a1~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a1~0 .extended_lut = "off";
defparam \counter1a1~0 .lut_mask = 64'h0700F8FF0000FFFF;
defparam \counter1a1~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a2~0 (
	.dataa(!int_rdempty),
	.datab(!rdreq),
	.datac(!counter1a01),
	.datad(!counter1a11),
	.datae(!counter1a21),
	.dataf(!\parity2~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a2~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a2~0 .extended_lut = "off";
defparam \counter1a2~0 .lut_mask = 64'h0002FFFD0000FFFF;
defparam \counter1a2~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a3~0 (
	.dataa(!valid_rdreq),
	.datab(!counter1a01),
	.datac(!counter1a11),
	.datad(!counter1a21),
	.datae(!counter1a31),
	.dataf(!\parity2~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a3~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a3~0 .extended_lut = "off";
defparam \counter1a3~0 .lut_mask = 64'h0010FFEF0000FFFF;
defparam \counter1a3~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a4~0 (
	.dataa(!valid_rdreq),
	.datab(!counter1a01),
	.datac(!counter1a11),
	.datad(!counter1a21),
	.datae(!counter1a41),
	.dataf(!\parity2~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a4~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a4~0 .extended_lut = "off";
defparam \counter1a4~0 .lut_mask = 64'h1000EFFF0000FFFF;
defparam \counter1a4~0 .shared_arith = "off";

endmodule

module fifo_clk_bridge_alt_synch_pipe_d9l (
	dffe8a_1,
	dffe8a_2,
	dffe8a_0,
	dffe8a_3,
	dffe8a_4,
	delayed_wrptr_g_1,
	delayed_wrptr_g_2,
	delayed_wrptr_g_0,
	delayed_wrptr_g_3,
	delayed_wrptr_g_4,
	clock)/* synthesis synthesis_greybox=0 */;
output 	dffe8a_1;
output 	dffe8a_2;
output 	dffe8a_0;
output 	dffe8a_3;
output 	dffe8a_4;
input 	delayed_wrptr_g_1;
input 	delayed_wrptr_g_2;
input 	delayed_wrptr_g_0;
input 	delayed_wrptr_g_3;
input 	delayed_wrptr_g_4;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



fifo_clk_bridge_dffpipe_uu8 dffpipe6(
	.dffe8a_1(dffe8a_1),
	.dffe8a_2(dffe8a_2),
	.dffe8a_0(dffe8a_0),
	.dffe8a_3(dffe8a_3),
	.dffe8a_4(dffe8a_4),
	.delayed_wrptr_g_1(delayed_wrptr_g_1),
	.delayed_wrptr_g_2(delayed_wrptr_g_2),
	.delayed_wrptr_g_0(delayed_wrptr_g_0),
	.delayed_wrptr_g_3(delayed_wrptr_g_3),
	.delayed_wrptr_g_4(delayed_wrptr_g_4),
	.clock(clock));

endmodule

module fifo_clk_bridge_dffpipe_uu8 (
	dffe8a_1,
	dffe8a_2,
	dffe8a_0,
	dffe8a_3,
	dffe8a_4,
	delayed_wrptr_g_1,
	delayed_wrptr_g_2,
	delayed_wrptr_g_0,
	delayed_wrptr_g_3,
	delayed_wrptr_g_4,
	clock)/* synthesis synthesis_greybox=0 */;
output 	dffe8a_1;
output 	dffe8a_2;
output 	dffe8a_0;
output 	dffe8a_3;
output 	dffe8a_4;
input 	delayed_wrptr_g_1;
input 	delayed_wrptr_g_2;
input 	delayed_wrptr_g_0;
input 	delayed_wrptr_g_3;
input 	delayed_wrptr_g_4;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \dffe7a[1]~q ;
wire \dffe7a[2]~q ;
wire \dffe7a[0]~q ;
wire \dffe7a[3]~q ;
wire \dffe7a[4]~q ;


dffeas \dffe8a[1] (
	.clk(clock),
	.d(\dffe7a[1]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_1),
	.prn(vcc));
defparam \dffe8a[1] .is_wysiwyg = "true";
defparam \dffe8a[1] .power_up = "low";
defparam \dffe8a[1] .x_on_violation = "off";

dffeas \dffe8a[2] (
	.clk(clock),
	.d(\dffe7a[2]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_2),
	.prn(vcc));
defparam \dffe8a[2] .is_wysiwyg = "true";
defparam \dffe8a[2] .power_up = "low";
defparam \dffe8a[2] .x_on_violation = "off";

dffeas \dffe8a[0] (
	.clk(clock),
	.d(\dffe7a[0]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_0),
	.prn(vcc));
defparam \dffe8a[0] .is_wysiwyg = "true";
defparam \dffe8a[0] .power_up = "low";
defparam \dffe8a[0] .x_on_violation = "off";

dffeas \dffe8a[3] (
	.clk(clock),
	.d(\dffe7a[3]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_3),
	.prn(vcc));
defparam \dffe8a[3] .is_wysiwyg = "true";
defparam \dffe8a[3] .power_up = "low";
defparam \dffe8a[3] .x_on_violation = "off";

dffeas \dffe8a[4] (
	.clk(clock),
	.d(\dffe7a[4]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_4),
	.prn(vcc));
defparam \dffe8a[4] .is_wysiwyg = "true";
defparam \dffe8a[4] .power_up = "low";
defparam \dffe8a[4] .x_on_violation = "off";

dffeas \dffe7a[1] (
	.clk(clock),
	.d(delayed_wrptr_g_1),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[1]~q ),
	.prn(vcc));
defparam \dffe7a[1] .is_wysiwyg = "true";
defparam \dffe7a[1] .power_up = "low";
defparam \dffe7a[1] .x_on_violation = "off";

dffeas \dffe7a[2] (
	.clk(clock),
	.d(delayed_wrptr_g_2),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[2]~q ),
	.prn(vcc));
defparam \dffe7a[2] .is_wysiwyg = "true";
defparam \dffe7a[2] .power_up = "low";
defparam \dffe7a[2] .x_on_violation = "off";

dffeas \dffe7a[0] (
	.clk(clock),
	.d(delayed_wrptr_g_0),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[0]~q ),
	.prn(vcc));
defparam \dffe7a[0] .is_wysiwyg = "true";
defparam \dffe7a[0] .power_up = "low";
defparam \dffe7a[0] .x_on_violation = "off";

dffeas \dffe7a[3] (
	.clk(clock),
	.d(delayed_wrptr_g_3),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[3]~q ),
	.prn(vcc));
defparam \dffe7a[3] .is_wysiwyg = "true";
defparam \dffe7a[3] .power_up = "low";
defparam \dffe7a[3] .x_on_violation = "off";

dffeas \dffe7a[4] (
	.clk(clock),
	.d(delayed_wrptr_g_4),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[4]~q ),
	.prn(vcc));
defparam \dffe7a[4] .is_wysiwyg = "true";
defparam \dffe7a[4] .power_up = "low";
defparam \dffe7a[4] .x_on_violation = "off";

endmodule

module fifo_clk_bridge_alt_synch_pipe_d9l_1 (
	rdptr_g_1,
	rdptr_g_2,
	rdptr_g_0,
	rdptr_g_3,
	rdptr_g_4,
	dffe8a_1,
	dffe8a_2,
	dffe8a_0,
	dffe8a_3,
	dffe8a_4,
	clock)/* synthesis synthesis_greybox=0 */;
input 	rdptr_g_1;
input 	rdptr_g_2;
input 	rdptr_g_0;
input 	rdptr_g_3;
input 	rdptr_g_4;
output 	dffe8a_1;
output 	dffe8a_2;
output 	dffe8a_0;
output 	dffe8a_3;
output 	dffe8a_4;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



fifo_clk_bridge_dffpipe_uu8_1 dffpipe6(
	.rdptr_g_1(rdptr_g_1),
	.rdptr_g_2(rdptr_g_2),
	.rdptr_g_0(rdptr_g_0),
	.rdptr_g_3(rdptr_g_3),
	.rdptr_g_4(rdptr_g_4),
	.dffe8a_1(dffe8a_1),
	.dffe8a_2(dffe8a_2),
	.dffe8a_0(dffe8a_0),
	.dffe8a_3(dffe8a_3),
	.dffe8a_4(dffe8a_4),
	.clock(clock));

endmodule

module fifo_clk_bridge_dffpipe_uu8_1 (
	rdptr_g_1,
	rdptr_g_2,
	rdptr_g_0,
	rdptr_g_3,
	rdptr_g_4,
	dffe8a_1,
	dffe8a_2,
	dffe8a_0,
	dffe8a_3,
	dffe8a_4,
	clock)/* synthesis synthesis_greybox=0 */;
input 	rdptr_g_1;
input 	rdptr_g_2;
input 	rdptr_g_0;
input 	rdptr_g_3;
input 	rdptr_g_4;
output 	dffe8a_1;
output 	dffe8a_2;
output 	dffe8a_0;
output 	dffe8a_3;
output 	dffe8a_4;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \dffe7a[1]~q ;
wire \dffe7a[2]~q ;
wire \dffe7a[0]~q ;
wire \dffe7a[3]~q ;
wire \dffe7a[4]~q ;


dffeas \dffe8a[1] (
	.clk(clock),
	.d(\dffe7a[1]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_1),
	.prn(vcc));
defparam \dffe8a[1] .is_wysiwyg = "true";
defparam \dffe8a[1] .power_up = "low";
defparam \dffe8a[1] .x_on_violation = "off";

dffeas \dffe8a[2] (
	.clk(clock),
	.d(\dffe7a[2]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_2),
	.prn(vcc));
defparam \dffe8a[2] .is_wysiwyg = "true";
defparam \dffe8a[2] .power_up = "low";
defparam \dffe8a[2] .x_on_violation = "off";

dffeas \dffe8a[0] (
	.clk(clock),
	.d(\dffe7a[0]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_0),
	.prn(vcc));
defparam \dffe8a[0] .is_wysiwyg = "true";
defparam \dffe8a[0] .power_up = "low";
defparam \dffe8a[0] .x_on_violation = "off";

dffeas \dffe8a[3] (
	.clk(clock),
	.d(\dffe7a[3]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_3),
	.prn(vcc));
defparam \dffe8a[3] .is_wysiwyg = "true";
defparam \dffe8a[3] .power_up = "low";
defparam \dffe8a[3] .x_on_violation = "off";

dffeas \dffe8a[4] (
	.clk(clock),
	.d(\dffe7a[4]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe8a_4),
	.prn(vcc));
defparam \dffe8a[4] .is_wysiwyg = "true";
defparam \dffe8a[4] .power_up = "low";
defparam \dffe8a[4] .x_on_violation = "off";

dffeas \dffe7a[1] (
	.clk(clock),
	.d(rdptr_g_1),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[1]~q ),
	.prn(vcc));
defparam \dffe7a[1] .is_wysiwyg = "true";
defparam \dffe7a[1] .power_up = "low";
defparam \dffe7a[1] .x_on_violation = "off";

dffeas \dffe7a[2] (
	.clk(clock),
	.d(rdptr_g_2),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[2]~q ),
	.prn(vcc));
defparam \dffe7a[2] .is_wysiwyg = "true";
defparam \dffe7a[2] .power_up = "low";
defparam \dffe7a[2] .x_on_violation = "off";

dffeas \dffe7a[0] (
	.clk(clock),
	.d(rdptr_g_0),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[0]~q ),
	.prn(vcc));
defparam \dffe7a[0] .is_wysiwyg = "true";
defparam \dffe7a[0] .power_up = "low";
defparam \dffe7a[0] .x_on_violation = "off";

dffeas \dffe7a[3] (
	.clk(clock),
	.d(rdptr_g_3),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[3]~q ),
	.prn(vcc));
defparam \dffe7a[3] .is_wysiwyg = "true";
defparam \dffe7a[3] .power_up = "low";
defparam \dffe7a[3] .x_on_violation = "off";

dffeas \dffe7a[4] (
	.clk(clock),
	.d(rdptr_g_4),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe7a[4]~q ),
	.prn(vcc));
defparam \dffe7a[4] .is_wysiwyg = "true";
defparam \dffe7a[4] .power_up = "low";
defparam \dffe7a[4] .x_on_violation = "off";

endmodule

module fifo_clk_bridge_altsyncram_l7a1 (
	q_b,
	wren_a,
	addressstall_b,
	clocken1,
	address_a,
	address_b,
	clock0,
	clock1,
	data_a)/* synthesis synthesis_greybox=0 */;
output 	[5:0] q_b;
input 	wren_a;
input 	addressstall_b;
input 	clocken1;
input 	[3:0] address_a;
input 	[3:0] address_b;
input 	clock0;
input 	clock1;
input 	[5:0] data_a;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;


wire [143:0] ram_block5a0_PORTBDATAOUT_bus;
wire [143:0] ram_block5a1_PORTBDATAOUT_bus;
wire [143:0] ram_block5a2_PORTBDATAOUT_bus;
wire [143:0] ram_block5a3_PORTBDATAOUT_bus;
wire [143:0] ram_block5a4_PORTBDATAOUT_bus;
wire [143:0] ram_block5a5_PORTBDATAOUT_bus;

assign q_b[0] = ram_block5a0_PORTBDATAOUT_bus[0];

assign q_b[1] = ram_block5a1_PORTBDATAOUT_bus[0];

assign q_b[2] = ram_block5a2_PORTBDATAOUT_bus[0];

assign q_b[3] = ram_block5a3_PORTBDATAOUT_bus[0];

assign q_b[4] = ram_block5a4_PORTBDATAOUT_bus[0];

assign q_b[5] = ram_block5a5_PORTBDATAOUT_bus[0];

twentynm_ram_block ram_block5a0(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(!addressstall_b),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(vcc),
	.ena1(addressstall_b),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[0]}),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block5a0_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block5a0.clk1_output_clock_enable = "ena1";
defparam ram_block5a0.data_interleave_offset_in_bits = 1;
defparam ram_block5a0.data_interleave_width_in_bits = 1;
defparam ram_block5a0.logical_ram_name = "fifo_clk_bridge_fifo_181_xtqoudq:fifo_0|dcfifo:dcfifo_component|dcfifo_9312:auto_generated|altsyncram_l7a1:fifo_ram|ALTSYNCRAM";
defparam ram_block5a0.mixed_port_feed_through_mode = "dont_care";
defparam ram_block5a0.operation_mode = "dual_port";
defparam ram_block5a0.port_a_address_clear = "none";
defparam ram_block5a0.port_a_address_width = 4;
defparam ram_block5a0.port_a_data_out_clear = "none";
defparam ram_block5a0.port_a_data_out_clock = "none";
defparam ram_block5a0.port_a_data_width = 1;
defparam ram_block5a0.port_a_first_address = 0;
defparam ram_block5a0.port_a_first_bit_number = 0;
defparam ram_block5a0.port_a_last_address = 15;
defparam ram_block5a0.port_a_logical_ram_depth = 16;
defparam ram_block5a0.port_a_logical_ram_width = 6;
defparam ram_block5a0.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a0.port_b_address_clear = "none";
defparam ram_block5a0.port_b_address_clock = "clock1";
defparam ram_block5a0.port_b_address_width = 4;
defparam ram_block5a0.port_b_data_out_clear = "none";
defparam ram_block5a0.port_b_data_out_clock = "clock1";
defparam ram_block5a0.port_b_data_width = 1;
defparam ram_block5a0.port_b_first_address = 0;
defparam ram_block5a0.port_b_first_bit_number = 0;
defparam ram_block5a0.port_b_last_address = 15;
defparam ram_block5a0.port_b_logical_ram_depth = 16;
defparam ram_block5a0.port_b_logical_ram_width = 6;
defparam ram_block5a0.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a0.port_b_read_enable_clock = "clock1";
defparam ram_block5a0.ram_block_type = "auto";

twentynm_ram_block ram_block5a1(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(!addressstall_b),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(vcc),
	.ena1(addressstall_b),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[1]}),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block5a1_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block5a1.clk1_output_clock_enable = "ena1";
defparam ram_block5a1.data_interleave_offset_in_bits = 1;
defparam ram_block5a1.data_interleave_width_in_bits = 1;
defparam ram_block5a1.logical_ram_name = "fifo_clk_bridge_fifo_181_xtqoudq:fifo_0|dcfifo:dcfifo_component|dcfifo_9312:auto_generated|altsyncram_l7a1:fifo_ram|ALTSYNCRAM";
defparam ram_block5a1.mixed_port_feed_through_mode = "dont_care";
defparam ram_block5a1.operation_mode = "dual_port";
defparam ram_block5a1.port_a_address_clear = "none";
defparam ram_block5a1.port_a_address_width = 4;
defparam ram_block5a1.port_a_data_out_clear = "none";
defparam ram_block5a1.port_a_data_out_clock = "none";
defparam ram_block5a1.port_a_data_width = 1;
defparam ram_block5a1.port_a_first_address = 0;
defparam ram_block5a1.port_a_first_bit_number = 1;
defparam ram_block5a1.port_a_last_address = 15;
defparam ram_block5a1.port_a_logical_ram_depth = 16;
defparam ram_block5a1.port_a_logical_ram_width = 6;
defparam ram_block5a1.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a1.port_b_address_clear = "none";
defparam ram_block5a1.port_b_address_clock = "clock1";
defparam ram_block5a1.port_b_address_width = 4;
defparam ram_block5a1.port_b_data_out_clear = "none";
defparam ram_block5a1.port_b_data_out_clock = "clock1";
defparam ram_block5a1.port_b_data_width = 1;
defparam ram_block5a1.port_b_first_address = 0;
defparam ram_block5a1.port_b_first_bit_number = 1;
defparam ram_block5a1.port_b_last_address = 15;
defparam ram_block5a1.port_b_logical_ram_depth = 16;
defparam ram_block5a1.port_b_logical_ram_width = 6;
defparam ram_block5a1.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a1.port_b_read_enable_clock = "clock1";
defparam ram_block5a1.ram_block_type = "auto";

twentynm_ram_block ram_block5a2(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(!addressstall_b),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(vcc),
	.ena1(addressstall_b),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[2]}),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block5a2_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block5a2.clk1_output_clock_enable = "ena1";
defparam ram_block5a2.data_interleave_offset_in_bits = 1;
defparam ram_block5a2.data_interleave_width_in_bits = 1;
defparam ram_block5a2.logical_ram_name = "fifo_clk_bridge_fifo_181_xtqoudq:fifo_0|dcfifo:dcfifo_component|dcfifo_9312:auto_generated|altsyncram_l7a1:fifo_ram|ALTSYNCRAM";
defparam ram_block5a2.mixed_port_feed_through_mode = "dont_care";
defparam ram_block5a2.operation_mode = "dual_port";
defparam ram_block5a2.port_a_address_clear = "none";
defparam ram_block5a2.port_a_address_width = 4;
defparam ram_block5a2.port_a_data_out_clear = "none";
defparam ram_block5a2.port_a_data_out_clock = "none";
defparam ram_block5a2.port_a_data_width = 1;
defparam ram_block5a2.port_a_first_address = 0;
defparam ram_block5a2.port_a_first_bit_number = 2;
defparam ram_block5a2.port_a_last_address = 15;
defparam ram_block5a2.port_a_logical_ram_depth = 16;
defparam ram_block5a2.port_a_logical_ram_width = 6;
defparam ram_block5a2.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a2.port_b_address_clear = "none";
defparam ram_block5a2.port_b_address_clock = "clock1";
defparam ram_block5a2.port_b_address_width = 4;
defparam ram_block5a2.port_b_data_out_clear = "none";
defparam ram_block5a2.port_b_data_out_clock = "clock1";
defparam ram_block5a2.port_b_data_width = 1;
defparam ram_block5a2.port_b_first_address = 0;
defparam ram_block5a2.port_b_first_bit_number = 2;
defparam ram_block5a2.port_b_last_address = 15;
defparam ram_block5a2.port_b_logical_ram_depth = 16;
defparam ram_block5a2.port_b_logical_ram_width = 6;
defparam ram_block5a2.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a2.port_b_read_enable_clock = "clock1";
defparam ram_block5a2.ram_block_type = "auto";

twentynm_ram_block ram_block5a3(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(!addressstall_b),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(vcc),
	.ena1(addressstall_b),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[3]}),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block5a3_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block5a3.clk1_output_clock_enable = "ena1";
defparam ram_block5a3.data_interleave_offset_in_bits = 1;
defparam ram_block5a3.data_interleave_width_in_bits = 1;
defparam ram_block5a3.logical_ram_name = "fifo_clk_bridge_fifo_181_xtqoudq:fifo_0|dcfifo:dcfifo_component|dcfifo_9312:auto_generated|altsyncram_l7a1:fifo_ram|ALTSYNCRAM";
defparam ram_block5a3.mixed_port_feed_through_mode = "dont_care";
defparam ram_block5a3.operation_mode = "dual_port";
defparam ram_block5a3.port_a_address_clear = "none";
defparam ram_block5a3.port_a_address_width = 4;
defparam ram_block5a3.port_a_data_out_clear = "none";
defparam ram_block5a3.port_a_data_out_clock = "none";
defparam ram_block5a3.port_a_data_width = 1;
defparam ram_block5a3.port_a_first_address = 0;
defparam ram_block5a3.port_a_first_bit_number = 3;
defparam ram_block5a3.port_a_last_address = 15;
defparam ram_block5a3.port_a_logical_ram_depth = 16;
defparam ram_block5a3.port_a_logical_ram_width = 6;
defparam ram_block5a3.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a3.port_b_address_clear = "none";
defparam ram_block5a3.port_b_address_clock = "clock1";
defparam ram_block5a3.port_b_address_width = 4;
defparam ram_block5a3.port_b_data_out_clear = "none";
defparam ram_block5a3.port_b_data_out_clock = "clock1";
defparam ram_block5a3.port_b_data_width = 1;
defparam ram_block5a3.port_b_first_address = 0;
defparam ram_block5a3.port_b_first_bit_number = 3;
defparam ram_block5a3.port_b_last_address = 15;
defparam ram_block5a3.port_b_logical_ram_depth = 16;
defparam ram_block5a3.port_b_logical_ram_width = 6;
defparam ram_block5a3.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a3.port_b_read_enable_clock = "clock1";
defparam ram_block5a3.ram_block_type = "auto";

twentynm_ram_block ram_block5a4(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(!addressstall_b),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(vcc),
	.ena1(addressstall_b),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[4]}),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block5a4_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block5a4.clk1_output_clock_enable = "ena1";
defparam ram_block5a4.data_interleave_offset_in_bits = 1;
defparam ram_block5a4.data_interleave_width_in_bits = 1;
defparam ram_block5a4.logical_ram_name = "fifo_clk_bridge_fifo_181_xtqoudq:fifo_0|dcfifo:dcfifo_component|dcfifo_9312:auto_generated|altsyncram_l7a1:fifo_ram|ALTSYNCRAM";
defparam ram_block5a4.mixed_port_feed_through_mode = "dont_care";
defparam ram_block5a4.operation_mode = "dual_port";
defparam ram_block5a4.port_a_address_clear = "none";
defparam ram_block5a4.port_a_address_width = 4;
defparam ram_block5a4.port_a_data_out_clear = "none";
defparam ram_block5a4.port_a_data_out_clock = "none";
defparam ram_block5a4.port_a_data_width = 1;
defparam ram_block5a4.port_a_first_address = 0;
defparam ram_block5a4.port_a_first_bit_number = 4;
defparam ram_block5a4.port_a_last_address = 15;
defparam ram_block5a4.port_a_logical_ram_depth = 16;
defparam ram_block5a4.port_a_logical_ram_width = 6;
defparam ram_block5a4.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a4.port_b_address_clear = "none";
defparam ram_block5a4.port_b_address_clock = "clock1";
defparam ram_block5a4.port_b_address_width = 4;
defparam ram_block5a4.port_b_data_out_clear = "none";
defparam ram_block5a4.port_b_data_out_clock = "clock1";
defparam ram_block5a4.port_b_data_width = 1;
defparam ram_block5a4.port_b_first_address = 0;
defparam ram_block5a4.port_b_first_bit_number = 4;
defparam ram_block5a4.port_b_last_address = 15;
defparam ram_block5a4.port_b_logical_ram_depth = 16;
defparam ram_block5a4.port_b_logical_ram_width = 6;
defparam ram_block5a4.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a4.port_b_read_enable_clock = "clock1";
defparam ram_block5a4.ram_block_type = "auto";

twentynm_ram_block ram_block5a5(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(!addressstall_b),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(vcc),
	.ena1(addressstall_b),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[5]}),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block5a5_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block5a5.clk1_output_clock_enable = "ena1";
defparam ram_block5a5.data_interleave_offset_in_bits = 1;
defparam ram_block5a5.data_interleave_width_in_bits = 1;
defparam ram_block5a5.logical_ram_name = "fifo_clk_bridge_fifo_181_xtqoudq:fifo_0|dcfifo:dcfifo_component|dcfifo_9312:auto_generated|altsyncram_l7a1:fifo_ram|ALTSYNCRAM";
defparam ram_block5a5.mixed_port_feed_through_mode = "dont_care";
defparam ram_block5a5.operation_mode = "dual_port";
defparam ram_block5a5.port_a_address_clear = "none";
defparam ram_block5a5.port_a_address_width = 4;
defparam ram_block5a5.port_a_data_out_clear = "none";
defparam ram_block5a5.port_a_data_out_clock = "none";
defparam ram_block5a5.port_a_data_width = 1;
defparam ram_block5a5.port_a_first_address = 0;
defparam ram_block5a5.port_a_first_bit_number = 5;
defparam ram_block5a5.port_a_last_address = 15;
defparam ram_block5a5.port_a_logical_ram_depth = 16;
defparam ram_block5a5.port_a_logical_ram_width = 6;
defparam ram_block5a5.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a5.port_b_address_clear = "none";
defparam ram_block5a5.port_b_address_clock = "clock1";
defparam ram_block5a5.port_b_address_width = 4;
defparam ram_block5a5.port_b_data_out_clear = "none";
defparam ram_block5a5.port_b_data_out_clock = "clock1";
defparam ram_block5a5.port_b_data_width = 1;
defparam ram_block5a5.port_b_first_address = 0;
defparam ram_block5a5.port_b_first_bit_number = 5;
defparam ram_block5a5.port_b_last_address = 15;
defparam ram_block5a5.port_b_logical_ram_depth = 16;
defparam ram_block5a5.port_b_logical_ram_width = 6;
defparam ram_block5a5.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block5a5.port_b_read_enable_clock = "clock1";
defparam ram_block5a5.ram_block_type = "auto";

endmodule

module fifo_clk_bridge_mux_ij7 (
	int_rdempty,
	counter1a0,
	counter1a1,
	counter1a2,
	dffe8a_1,
	rdptr_g_1,
	dffe8a_2,
	dffe8a_0,
	rdptr_g_2,
	rdptr_g_0,
	l1_w0_n0_mux_dataout,
	rdreq)/* synthesis synthesis_greybox=0 */;
input 	int_rdempty;
input 	counter1a0;
input 	counter1a1;
input 	counter1a2;
input 	dffe8a_1;
input 	rdptr_g_1;
input 	dffe8a_2;
input 	dffe8a_0;
input 	rdptr_g_2;
input 	rdptr_g_0;
output 	l1_w0_n0_mux_dataout;
input 	rdreq;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \l1_w0_n0_mux_dataout~0_combout ;
wire \l1_w0_n0_mux_dataout~1_combout ;


twentynm_lcell_comb \l1_w0_n0_mux_dataout~2 (
	.dataa(!int_rdempty),
	.datab(!rdreq),
	.datac(!dffe8a_1),
	.datad(!rdptr_g_1),
	.datae(!\l1_w0_n0_mux_dataout~0_combout ),
	.dataf(!\l1_w0_n0_mux_dataout~1_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(l1_w0_n0_mux_dataout),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~2 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~2 .lut_mask = 64'hFFFFDDDD2FF20DD0;
defparam \l1_w0_n0_mux_dataout~2 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~0 (
	.dataa(!counter1a0),
	.datab(!counter1a1),
	.datac(!counter1a2),
	.datad(!dffe8a_2),
	.datae(!dffe8a_0),
	.dataf(!dffe8a_1),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~0 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~0 .lut_mask = 64'h4004800810012002;
defparam \l1_w0_n0_mux_dataout~0 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~1 (
	.dataa(!dffe8a_2),
	.datab(!dffe8a_0),
	.datac(!rdptr_g_2),
	.datad(!rdptr_g_0),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~1 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~1 .lut_mask = 64'h8421842184218421;
defparam \l1_w0_n0_mux_dataout~1 .shared_arith = "off";

endmodule

module fifo_clk_bridge_mux_ij7_1 (
	rdemp_eq_comp_lsb_aeb,
	rdemp_eq_comp_msb_aeb,
	counter1a3,
	counter1a4,
	rdptr_g_3,
	dffe8a_3,
	rdptr_g_4,
	dffe8a_4,
	l1_w0_n0_mux_dataout,
	rdreq)/* synthesis synthesis_greybox=0 */;
input 	rdemp_eq_comp_lsb_aeb;
input 	rdemp_eq_comp_msb_aeb;
input 	counter1a3;
input 	counter1a4;
input 	rdptr_g_3;
input 	dffe8a_3;
input 	rdptr_g_4;
input 	dffe8a_4;
output 	l1_w0_n0_mux_dataout;
input 	rdreq;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \l1_w0_n0_mux_dataout~1_combout ;
wire \l1_w0_n0_mux_dataout~2_combout ;


twentynm_lcell_comb \l1_w0_n0_mux_dataout~0 (
	.dataa(!rdreq),
	.datab(!rdemp_eq_comp_lsb_aeb),
	.datac(!rdemp_eq_comp_msb_aeb),
	.datad(!\l1_w0_n0_mux_dataout~1_combout ),
	.datae(!\l1_w0_n0_mux_dataout~2_combout ),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(l1_w0_n0_mux_dataout),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~0 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~0 .lut_mask = 64'hFFEA1500FFEA1500;
defparam \l1_w0_n0_mux_dataout~0 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~1 (
	.dataa(!dffe8a_3),
	.datab(!dffe8a_4),
	.datac(!counter1a3),
	.datad(!counter1a4),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~1 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~1 .lut_mask = 64'h8421842184218421;
defparam \l1_w0_n0_mux_dataout~1 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~2 (
	.dataa(!rdptr_g_3),
	.datab(!dffe8a_3),
	.datac(!rdptr_g_4),
	.datad(!dffe8a_4),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~2_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~2 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~2 .lut_mask = 64'h9009900990099009;
defparam \l1_w0_n0_mux_dataout~2 .shared_arith = "off";

endmodule

module fifo_clk_bridge_mux_ij7_2 (
	int_wrfull,
	wrptr_g_0,
	wrptr_g_1,
	wrptr_g_2,
	dffe8a_1,
	counter3a2,
	dffe8a_2,
	counter3a0,
	dffe8a_0,
	counter3a1,
	l1_w0_n0_mux_dataout,
	wrreq)/* synthesis synthesis_greybox=0 */;
input 	int_wrfull;
input 	wrptr_g_0;
input 	wrptr_g_1;
input 	wrptr_g_2;
input 	dffe8a_1;
input 	counter3a2;
input 	dffe8a_2;
input 	counter3a0;
input 	dffe8a_0;
input 	counter3a1;
output 	l1_w0_n0_mux_dataout;
input 	wrreq;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \l1_w0_n0_mux_dataout~0_combout ;
wire \l1_w0_n0_mux_dataout~1_combout ;


twentynm_lcell_comb \l1_w0_n0_mux_dataout~2 (
	.dataa(!int_wrfull),
	.datab(!wrreq),
	.datac(!wrptr_g_1),
	.datad(!dffe8a_1),
	.datae(!\l1_w0_n0_mux_dataout~0_combout ),
	.dataf(!\l1_w0_n0_mux_dataout~1_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(l1_w0_n0_mux_dataout),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~2 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~2 .lut_mask = 64'h00002222D00DF22F;
defparam \l1_w0_n0_mux_dataout~2 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~0 (
	.dataa(!counter3a2),
	.datab(!dffe8a_2),
	.datac(!counter3a0),
	.datad(!dffe8a_0),
	.datae(!counter3a1),
	.dataf(!dffe8a_1),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~0 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~0 .lut_mask = 64'h0990000000000990;
defparam \l1_w0_n0_mux_dataout~0 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~1 (
	.dataa(!wrptr_g_0),
	.datab(!wrptr_g_2),
	.datac(!dffe8a_2),
	.datad(!dffe8a_0),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~1 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~1 .lut_mask = 64'h8241824182418241;
defparam \l1_w0_n0_mux_dataout~1 .shared_arith = "off";

endmodule

module fifo_clk_bridge_mux_ij7_3 (
	int_wrfull,
	wrptr_g_4,
	wrptr_g_3,
	counter3a3,
	dffe8a_3,
	counter3a4,
	dffe8a_4,
	l1_w0_n0_mux_dataout,
	wrreq)/* synthesis synthesis_greybox=0 */;
input 	int_wrfull;
input 	wrptr_g_4;
input 	wrptr_g_3;
input 	counter3a3;
input 	dffe8a_3;
input 	counter3a4;
input 	dffe8a_4;
output 	l1_w0_n0_mux_dataout;
input 	wrreq;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \l1_w0_n0_mux_dataout~0_combout ;
wire \l1_w0_n0_mux_dataout~1_combout ;


twentynm_lcell_comb \l1_w0_n0_mux_dataout~2 (
	.dataa(!int_wrfull),
	.datab(!wrreq),
	.datac(!\l1_w0_n0_mux_dataout~0_combout ),
	.datad(!\l1_w0_n0_mux_dataout~1_combout ),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(l1_w0_n0_mux_dataout),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~2 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~2 .lut_mask = 64'h02DF02DF02DF02DF;
defparam \l1_w0_n0_mux_dataout~2 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~0 (
	.dataa(!counter3a3),
	.datab(!dffe8a_3),
	.datac(!counter3a4),
	.datad(!dffe8a_4),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~0 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~0 .lut_mask = 64'h0660066006600660;
defparam \l1_w0_n0_mux_dataout~0 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~1 (
	.dataa(!wrptr_g_4),
	.datab(!wrptr_g_3),
	.datac(!dffe8a_3),
	.datad(!dffe8a_4),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~1 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~1 .lut_mask = 64'h1428142814281428;
defparam \l1_w0_n0_mux_dataout~1 .shared_arith = "off";

endmodule
