// fifo_clk_bridge.v

// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module fifo_clk_bridge (
		input  wire [5:0] data,    //  fifo_input.datain
		input  wire       wrreq,   //            .wrreq
		input  wire       rdreq,   //            .rdreq
		input  wire       wrclk,   //            .wrclk
		input  wire       rdclk,   //            .rdclk
		output wire [5:0] q,       // fifo_output.dataout
		output wire       rdempty, //            .rdempty
		output wire       wrfull   //            .wrfull
	);

	fifo_clk_bridge_fifo_181_xtqoudq fifo_0 (
		.data    (data),    //  fifo_input.datain
		.wrreq   (wrreq),   //            .wrreq
		.rdreq   (rdreq),   //            .rdreq
		.wrclk   (wrclk),   //            .wrclk
		.rdclk   (rdclk),   //            .rdclk
		.q       (q),       // fifo_output.dataout
		.rdempty (rdempty), //            .rdempty
		.wrfull  (wrfull)   //            .wrfull
	);

endmodule
