
module fifo_clk_bridge (
	data,
	wrreq,
	rdreq,
	wrclk,
	rdclk,
	q,
	rdempty,
	wrfull);	

	input	[5:0]	data;
	input		wrreq;
	input		rdreq;
	input		wrclk;
	input		rdclk;
	output	[5:0]	q;
	output		rdempty;
	output		wrfull;
endmodule
