// dp_6bit.v

// Generated using ACDS version 18.1 625

`timescale 1 ps / 1 ps
module dp_6bit (
		input  wire [5:0]  data,      //  ram_input.datain
		input  wire [11:0] wraddress, //           .wraddress
		input  wire [11:0] rdaddress, //           .rdaddress
		input  wire        wren,      //           .wren
		input  wire        wrclock,   //           .wrclock
		input  wire        rdclock,   //           .rdclock
		output wire [5:0]  q          // ram_output.dataout
	);

	dp_6bit_ram_2port_181_qjvansq ram_2port_0 (
		.data      (data),      //  ram_input.datain
		.wraddress (wraddress), //           .wraddress
		.rdaddress (rdaddress), //           .rdaddress
		.wren      (wren),      //           .wren
		.wrclock   (wrclock),   //           .wrclock
		.rdclock   (rdclock),   //           .rdclock
		.q         (q)          // ram_output.dataout
	);

endmodule
