// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition"

// DATE "04/09/2019 16:22:28"

// 
// Device: Altera 10AX016E3F27E1HG Package FBGA672
// 

// 
// This greybox netlist file is for third party Synthesis Tools
// for timing and resource estimation only.
// 


module dp_6bit (
	data,
	wraddress,
	rdaddress,
	wren,
	wrclock,
	rdclock,
	q)/* synthesis synthesis_greybox=0 */;
input 	[5:0] data;
input 	[11:0] wraddress;
input 	[11:0] rdaddress;
input 	wren;
input 	wrclock;
input 	rdclock;
output 	[5:0] q;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[0] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[1] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[2] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[3] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[4] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[5] ;
wire \wren~input_o ;
wire \wrclock~input_o ;
wire \rdclock~input_o ;
wire \data[0]~input_o ;
wire \wraddress[0]~input_o ;
wire \wraddress[1]~input_o ;
wire \wraddress[2]~input_o ;
wire \wraddress[3]~input_o ;
wire \wraddress[4]~input_o ;
wire \wraddress[5]~input_o ;
wire \wraddress[6]~input_o ;
wire \wraddress[7]~input_o ;
wire \wraddress[8]~input_o ;
wire \wraddress[9]~input_o ;
wire \wraddress[10]~input_o ;
wire \wraddress[11]~input_o ;
wire \rdaddress[0]~input_o ;
wire \rdaddress[1]~input_o ;
wire \rdaddress[2]~input_o ;
wire \rdaddress[3]~input_o ;
wire \rdaddress[4]~input_o ;
wire \rdaddress[5]~input_o ;
wire \rdaddress[6]~input_o ;
wire \rdaddress[7]~input_o ;
wire \rdaddress[8]~input_o ;
wire \rdaddress[9]~input_o ;
wire \rdaddress[10]~input_o ;
wire \rdaddress[11]~input_o ;
wire \data[1]~input_o ;
wire \data[2]~input_o ;
wire \data[3]~input_o ;
wire \data[4]~input_o ;
wire \data[5]~input_o ;


dp_6bit_dp_6bit_ram_2port_181_qjvansq ram_2port_0(
	.q_b_0(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[0] ),
	.q_b_1(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[1] ),
	.q_b_2(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[2] ),
	.q_b_3(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[3] ),
	.q_b_4(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[4] ),
	.q_b_5(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[5] ),
	.wren(\wren~input_o ),
	.wrclock(\wrclock~input_o ),
	.rdclock(\rdclock~input_o ),
	.data_0(\data[0]~input_o ),
	.wraddress_0(\wraddress[0]~input_o ),
	.wraddress_1(\wraddress[1]~input_o ),
	.wraddress_2(\wraddress[2]~input_o ),
	.wraddress_3(\wraddress[3]~input_o ),
	.wraddress_4(\wraddress[4]~input_o ),
	.wraddress_5(\wraddress[5]~input_o ),
	.wraddress_6(\wraddress[6]~input_o ),
	.wraddress_7(\wraddress[7]~input_o ),
	.wraddress_8(\wraddress[8]~input_o ),
	.wraddress_9(\wraddress[9]~input_o ),
	.wraddress_10(\wraddress[10]~input_o ),
	.wraddress_11(\wraddress[11]~input_o ),
	.rdaddress_0(\rdaddress[0]~input_o ),
	.rdaddress_1(\rdaddress[1]~input_o ),
	.rdaddress_2(\rdaddress[2]~input_o ),
	.rdaddress_3(\rdaddress[3]~input_o ),
	.rdaddress_4(\rdaddress[4]~input_o ),
	.rdaddress_5(\rdaddress[5]~input_o ),
	.rdaddress_6(\rdaddress[6]~input_o ),
	.rdaddress_7(\rdaddress[7]~input_o ),
	.rdaddress_8(\rdaddress[8]~input_o ),
	.rdaddress_9(\rdaddress[9]~input_o ),
	.rdaddress_10(\rdaddress[10]~input_o ),
	.rdaddress_11(\rdaddress[11]~input_o ),
	.data_1(\data[1]~input_o ),
	.data_2(\data[2]~input_o ),
	.data_3(\data[3]~input_o ),
	.data_4(\data[4]~input_o ),
	.data_5(\data[5]~input_o ));

assign \wren~input_o  = wren;

assign \wrclock~input_o  = wrclock;

assign \rdclock~input_o  = rdclock;

assign \data[0]~input_o  = data[0];

assign \wraddress[0]~input_o  = wraddress[0];

assign \wraddress[1]~input_o  = wraddress[1];

assign \wraddress[2]~input_o  = wraddress[2];

assign \wraddress[3]~input_o  = wraddress[3];

assign \wraddress[4]~input_o  = wraddress[4];

assign \wraddress[5]~input_o  = wraddress[5];

assign \wraddress[6]~input_o  = wraddress[6];

assign \wraddress[7]~input_o  = wraddress[7];

assign \wraddress[8]~input_o  = wraddress[8];

assign \wraddress[9]~input_o  = wraddress[9];

assign \wraddress[10]~input_o  = wraddress[10];

assign \wraddress[11]~input_o  = wraddress[11];

assign \rdaddress[0]~input_o  = rdaddress[0];

assign \rdaddress[1]~input_o  = rdaddress[1];

assign \rdaddress[2]~input_o  = rdaddress[2];

assign \rdaddress[3]~input_o  = rdaddress[3];

assign \rdaddress[4]~input_o  = rdaddress[4];

assign \rdaddress[5]~input_o  = rdaddress[5];

assign \rdaddress[6]~input_o  = rdaddress[6];

assign \rdaddress[7]~input_o  = rdaddress[7];

assign \rdaddress[8]~input_o  = rdaddress[8];

assign \rdaddress[9]~input_o  = rdaddress[9];

assign \rdaddress[10]~input_o  = rdaddress[10];

assign \rdaddress[11]~input_o  = rdaddress[11];

assign \data[1]~input_o  = data[1];

assign \data[2]~input_o  = data[2];

assign \data[3]~input_o  = data[3];

assign \data[4]~input_o  = data[4];

assign \data[5]~input_o  = data[5];

assign q[0] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[0] ;

assign q[1] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[1] ;

assign q[2] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[2] ;

assign q[3] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[3] ;

assign q[4] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[4] ;

assign q[5] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[5] ;

endmodule

module dp_6bit_dp_6bit_ram_2port_181_qjvansq (
	q_b_0,
	q_b_1,
	q_b_2,
	q_b_3,
	q_b_4,
	q_b_5,
	wren,
	wrclock,
	rdclock,
	data_0,
	wraddress_0,
	wraddress_1,
	wraddress_2,
	wraddress_3,
	wraddress_4,
	wraddress_5,
	wraddress_6,
	wraddress_7,
	wraddress_8,
	wraddress_9,
	wraddress_10,
	wraddress_11,
	rdaddress_0,
	rdaddress_1,
	rdaddress_2,
	rdaddress_3,
	rdaddress_4,
	rdaddress_5,
	rdaddress_6,
	rdaddress_7,
	rdaddress_8,
	rdaddress_9,
	rdaddress_10,
	rdaddress_11,
	data_1,
	data_2,
	data_3,
	data_4,
	data_5)/* synthesis synthesis_greybox=0 */;
output 	q_b_0;
output 	q_b_1;
output 	q_b_2;
output 	q_b_3;
output 	q_b_4;
output 	q_b_5;
input 	wren;
input 	wrclock;
input 	rdclock;
input 	data_0;
input 	wraddress_0;
input 	wraddress_1;
input 	wraddress_2;
input 	wraddress_3;
input 	wraddress_4;
input 	wraddress_5;
input 	wraddress_6;
input 	wraddress_7;
input 	wraddress_8;
input 	wraddress_9;
input 	wraddress_10;
input 	wraddress_11;
input 	rdaddress_0;
input 	rdaddress_1;
input 	rdaddress_2;
input 	rdaddress_3;
input 	rdaddress_4;
input 	rdaddress_5;
input 	rdaddress_6;
input 	rdaddress_7;
input 	rdaddress_8;
input 	rdaddress_9;
input 	rdaddress_10;
input 	rdaddress_11;
input 	data_1;
input 	data_2;
input 	data_3;
input 	data_4;
input 	data_5;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



dp_6bit_altera_syncram altera_syncram_component(
	.q_b({q_b_5,q_b_4,q_b_3,q_b_2,q_b_1,q_b_0}),
	.wren_a(wren),
	.clock0(wrclock),
	.clock1(rdclock),
	.data_a({data_5,data_4,data_3,data_2,data_1,data_0}),
	.address_a({wraddress_11,wraddress_10,wraddress_9,wraddress_8,wraddress_7,wraddress_6,wraddress_5,wraddress_4,wraddress_3,wraddress_2,wraddress_1,wraddress_0}),
	.address_b({rdaddress_11,rdaddress_10,rdaddress_9,rdaddress_8,rdaddress_7,rdaddress_6,rdaddress_5,rdaddress_4,rdaddress_3,rdaddress_2,rdaddress_1,rdaddress_0}));

endmodule

module dp_6bit_altera_syncram (
	q_b,
	wren_a,
	clock0,
	clock1,
	data_a,
	address_a,
	address_b)/* synthesis synthesis_greybox=0 */;
output 	[5:0] q_b;
input 	wren_a;
input 	clock0;
input 	clock1;
input 	[5:0] data_a;
input 	[11:0] address_a;
input 	[11:0] address_b;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



dp_6bit_altera_syncram_n1s1 auto_generated(
	.q_b({q_b[5],q_b[4],q_b[3],q_b[2],q_b[1],q_b[0]}),
	.wren_a(wren_a),
	.clock0(clock0),
	.clock1(clock1),
	.data_a({data_a[5],data_a[4],data_a[3],data_a[2],data_a[1],data_a[0]}),
	.address_a({address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.address_b({address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}));

endmodule

module dp_6bit_altera_syncram_n1s1 (
	q_b,
	wren_a,
	clock0,
	clock1,
	data_a,
	address_a,
	address_b)/* synthesis synthesis_greybox=0 */;
output 	[5:0] q_b;
input 	wren_a;
input 	clock0;
input 	clock1;
input 	[5:0] data_a;
input 	[11:0] address_a;
input 	[11:0] address_b;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



dp_6bit_altsyncram_jg84 altsyncram1(
	.q_b({q_b[5],q_b[4],q_b[3],q_b[2],q_b[1],q_b[0]}),
	.wren_a(wren_a),
	.clock0(clock0),
	.clock1(clock1),
	.data_a({data_a[5],data_a[4],data_a[3],data_a[2],data_a[1],data_a[0]}),
	.address_a({address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.address_b({address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}));

endmodule

module dp_6bit_altsyncram_jg84 (
	q_b,
	wren_a,
	clock0,
	clock1,
	data_a,
	address_a,
	address_b)/* synthesis synthesis_greybox=0 */;
output 	[5:0] q_b;
input 	wren_a;
input 	clock0;
input 	clock1;
input 	[5:0] data_a;
input 	[11:0] address_a;
input 	[11:0] address_b;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;


wire [143:0] ram_block2a0_PORTBDATAOUT_bus;
wire [143:0] ram_block2a1_PORTBDATAOUT_bus;
wire [143:0] ram_block2a2_PORTBDATAOUT_bus;
wire [143:0] ram_block2a3_PORTBDATAOUT_bus;
wire [143:0] ram_block2a4_PORTBDATAOUT_bus;
wire [143:0] ram_block2a5_PORTBDATAOUT_bus;

assign q_b[0] = ram_block2a0_PORTBDATAOUT_bus[0];

assign q_b[1] = ram_block2a1_PORTBDATAOUT_bus[0];

assign q_b[2] = ram_block2a2_PORTBDATAOUT_bus[0];

assign q_b[3] = ram_block2a3_PORTBDATAOUT_bus[0];

assign q_b[4] = ram_block2a4_PORTBDATAOUT_bus[0];

assign q_b[5] = ram_block2a5_PORTBDATAOUT_bus[0];

twentynm_ram_block ram_block2a0(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[0]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a0_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a0.clk0_core_clock_enable = "ena0";
defparam ram_block2a0.data_interleave_offset_in_bits = 1;
defparam ram_block2a0.data_interleave_width_in_bits = 1;
defparam ram_block2a0.logical_ram_name = "dp_6bit_ram_2port_181_qjvansq:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_n1s1:auto_generated|altsyncram_jg84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a0.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a0.operation_mode = "dual_port";
defparam ram_block2a0.port_a_address_clear = "none";
defparam ram_block2a0.port_a_address_width = 12;
defparam ram_block2a0.port_a_data_out_clear = "none";
defparam ram_block2a0.port_a_data_out_clock = "none";
defparam ram_block2a0.port_a_data_width = 1;
defparam ram_block2a0.port_a_first_address = 0;
defparam ram_block2a0.port_a_first_bit_number = 0;
defparam ram_block2a0.port_a_last_address = 4095;
defparam ram_block2a0.port_a_logical_ram_depth = 4096;
defparam ram_block2a0.port_a_logical_ram_width = 6;
defparam ram_block2a0.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a0.port_b_address_clear = "none";
defparam ram_block2a0.port_b_address_clock = "clock1";
defparam ram_block2a0.port_b_address_width = 12;
defparam ram_block2a0.port_b_data_out_clear = "none";
defparam ram_block2a0.port_b_data_out_clock = "clock1";
defparam ram_block2a0.port_b_data_width = 1;
defparam ram_block2a0.port_b_first_address = 0;
defparam ram_block2a0.port_b_first_bit_number = 0;
defparam ram_block2a0.port_b_last_address = 4095;
defparam ram_block2a0.port_b_logical_ram_depth = 4096;
defparam ram_block2a0.port_b_logical_ram_width = 6;
defparam ram_block2a0.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a0.port_b_read_enable_clock = "clock1";
defparam ram_block2a0.ram_block_type = "auto";

twentynm_ram_block ram_block2a1(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[1]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a1_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a1.clk0_core_clock_enable = "ena0";
defparam ram_block2a1.data_interleave_offset_in_bits = 1;
defparam ram_block2a1.data_interleave_width_in_bits = 1;
defparam ram_block2a1.logical_ram_name = "dp_6bit_ram_2port_181_qjvansq:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_n1s1:auto_generated|altsyncram_jg84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a1.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a1.operation_mode = "dual_port";
defparam ram_block2a1.port_a_address_clear = "none";
defparam ram_block2a1.port_a_address_width = 12;
defparam ram_block2a1.port_a_data_out_clear = "none";
defparam ram_block2a1.port_a_data_out_clock = "none";
defparam ram_block2a1.port_a_data_width = 1;
defparam ram_block2a1.port_a_first_address = 0;
defparam ram_block2a1.port_a_first_bit_number = 1;
defparam ram_block2a1.port_a_last_address = 4095;
defparam ram_block2a1.port_a_logical_ram_depth = 4096;
defparam ram_block2a1.port_a_logical_ram_width = 6;
defparam ram_block2a1.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a1.port_b_address_clear = "none";
defparam ram_block2a1.port_b_address_clock = "clock1";
defparam ram_block2a1.port_b_address_width = 12;
defparam ram_block2a1.port_b_data_out_clear = "none";
defparam ram_block2a1.port_b_data_out_clock = "clock1";
defparam ram_block2a1.port_b_data_width = 1;
defparam ram_block2a1.port_b_first_address = 0;
defparam ram_block2a1.port_b_first_bit_number = 1;
defparam ram_block2a1.port_b_last_address = 4095;
defparam ram_block2a1.port_b_logical_ram_depth = 4096;
defparam ram_block2a1.port_b_logical_ram_width = 6;
defparam ram_block2a1.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a1.port_b_read_enable_clock = "clock1";
defparam ram_block2a1.ram_block_type = "auto";

twentynm_ram_block ram_block2a2(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[2]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a2_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a2.clk0_core_clock_enable = "ena0";
defparam ram_block2a2.data_interleave_offset_in_bits = 1;
defparam ram_block2a2.data_interleave_width_in_bits = 1;
defparam ram_block2a2.logical_ram_name = "dp_6bit_ram_2port_181_qjvansq:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_n1s1:auto_generated|altsyncram_jg84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a2.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a2.operation_mode = "dual_port";
defparam ram_block2a2.port_a_address_clear = "none";
defparam ram_block2a2.port_a_address_width = 12;
defparam ram_block2a2.port_a_data_out_clear = "none";
defparam ram_block2a2.port_a_data_out_clock = "none";
defparam ram_block2a2.port_a_data_width = 1;
defparam ram_block2a2.port_a_first_address = 0;
defparam ram_block2a2.port_a_first_bit_number = 2;
defparam ram_block2a2.port_a_last_address = 4095;
defparam ram_block2a2.port_a_logical_ram_depth = 4096;
defparam ram_block2a2.port_a_logical_ram_width = 6;
defparam ram_block2a2.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a2.port_b_address_clear = "none";
defparam ram_block2a2.port_b_address_clock = "clock1";
defparam ram_block2a2.port_b_address_width = 12;
defparam ram_block2a2.port_b_data_out_clear = "none";
defparam ram_block2a2.port_b_data_out_clock = "clock1";
defparam ram_block2a2.port_b_data_width = 1;
defparam ram_block2a2.port_b_first_address = 0;
defparam ram_block2a2.port_b_first_bit_number = 2;
defparam ram_block2a2.port_b_last_address = 4095;
defparam ram_block2a2.port_b_logical_ram_depth = 4096;
defparam ram_block2a2.port_b_logical_ram_width = 6;
defparam ram_block2a2.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a2.port_b_read_enable_clock = "clock1";
defparam ram_block2a2.ram_block_type = "auto";

twentynm_ram_block ram_block2a3(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[3]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a3_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a3.clk0_core_clock_enable = "ena0";
defparam ram_block2a3.data_interleave_offset_in_bits = 1;
defparam ram_block2a3.data_interleave_width_in_bits = 1;
defparam ram_block2a3.logical_ram_name = "dp_6bit_ram_2port_181_qjvansq:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_n1s1:auto_generated|altsyncram_jg84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a3.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a3.operation_mode = "dual_port";
defparam ram_block2a3.port_a_address_clear = "none";
defparam ram_block2a3.port_a_address_width = 12;
defparam ram_block2a3.port_a_data_out_clear = "none";
defparam ram_block2a3.port_a_data_out_clock = "none";
defparam ram_block2a3.port_a_data_width = 1;
defparam ram_block2a3.port_a_first_address = 0;
defparam ram_block2a3.port_a_first_bit_number = 3;
defparam ram_block2a3.port_a_last_address = 4095;
defparam ram_block2a3.port_a_logical_ram_depth = 4096;
defparam ram_block2a3.port_a_logical_ram_width = 6;
defparam ram_block2a3.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a3.port_b_address_clear = "none";
defparam ram_block2a3.port_b_address_clock = "clock1";
defparam ram_block2a3.port_b_address_width = 12;
defparam ram_block2a3.port_b_data_out_clear = "none";
defparam ram_block2a3.port_b_data_out_clock = "clock1";
defparam ram_block2a3.port_b_data_width = 1;
defparam ram_block2a3.port_b_first_address = 0;
defparam ram_block2a3.port_b_first_bit_number = 3;
defparam ram_block2a3.port_b_last_address = 4095;
defparam ram_block2a3.port_b_logical_ram_depth = 4096;
defparam ram_block2a3.port_b_logical_ram_width = 6;
defparam ram_block2a3.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a3.port_b_read_enable_clock = "clock1";
defparam ram_block2a3.ram_block_type = "auto";

twentynm_ram_block ram_block2a4(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[4]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a4_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a4.clk0_core_clock_enable = "ena0";
defparam ram_block2a4.data_interleave_offset_in_bits = 1;
defparam ram_block2a4.data_interleave_width_in_bits = 1;
defparam ram_block2a4.logical_ram_name = "dp_6bit_ram_2port_181_qjvansq:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_n1s1:auto_generated|altsyncram_jg84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a4.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a4.operation_mode = "dual_port";
defparam ram_block2a4.port_a_address_clear = "none";
defparam ram_block2a4.port_a_address_width = 12;
defparam ram_block2a4.port_a_data_out_clear = "none";
defparam ram_block2a4.port_a_data_out_clock = "none";
defparam ram_block2a4.port_a_data_width = 1;
defparam ram_block2a4.port_a_first_address = 0;
defparam ram_block2a4.port_a_first_bit_number = 4;
defparam ram_block2a4.port_a_last_address = 4095;
defparam ram_block2a4.port_a_logical_ram_depth = 4096;
defparam ram_block2a4.port_a_logical_ram_width = 6;
defparam ram_block2a4.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a4.port_b_address_clear = "none";
defparam ram_block2a4.port_b_address_clock = "clock1";
defparam ram_block2a4.port_b_address_width = 12;
defparam ram_block2a4.port_b_data_out_clear = "none";
defparam ram_block2a4.port_b_data_out_clock = "clock1";
defparam ram_block2a4.port_b_data_width = 1;
defparam ram_block2a4.port_b_first_address = 0;
defparam ram_block2a4.port_b_first_bit_number = 4;
defparam ram_block2a4.port_b_last_address = 4095;
defparam ram_block2a4.port_b_logical_ram_depth = 4096;
defparam ram_block2a4.port_b_logical_ram_width = 6;
defparam ram_block2a4.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a4.port_b_read_enable_clock = "clock1";
defparam ram_block2a4.ram_block_type = "auto";

twentynm_ram_block ram_block2a5(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[5]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a5_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a5.clk0_core_clock_enable = "ena0";
defparam ram_block2a5.data_interleave_offset_in_bits = 1;
defparam ram_block2a5.data_interleave_width_in_bits = 1;
defparam ram_block2a5.logical_ram_name = "dp_6bit_ram_2port_181_qjvansq:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_n1s1:auto_generated|altsyncram_jg84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a5.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a5.operation_mode = "dual_port";
defparam ram_block2a5.port_a_address_clear = "none";
defparam ram_block2a5.port_a_address_width = 12;
defparam ram_block2a5.port_a_data_out_clear = "none";
defparam ram_block2a5.port_a_data_out_clock = "none";
defparam ram_block2a5.port_a_data_width = 1;
defparam ram_block2a5.port_a_first_address = 0;
defparam ram_block2a5.port_a_first_bit_number = 5;
defparam ram_block2a5.port_a_last_address = 4095;
defparam ram_block2a5.port_a_logical_ram_depth = 4096;
defparam ram_block2a5.port_a_logical_ram_width = 6;
defparam ram_block2a5.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a5.port_b_address_clear = "none";
defparam ram_block2a5.port_b_address_clock = "clock1";
defparam ram_block2a5.port_b_address_width = 12;
defparam ram_block2a5.port_b_data_out_clear = "none";
defparam ram_block2a5.port_b_data_out_clock = "clock1";
defparam ram_block2a5.port_b_data_width = 1;
defparam ram_block2a5.port_b_first_address = 0;
defparam ram_block2a5.port_b_first_bit_number = 5;
defparam ram_block2a5.port_b_last_address = 4095;
defparam ram_block2a5.port_b_logical_ram_depth = 4096;
defparam ram_block2a5.port_b_logical_ram_width = 6;
defparam ram_block2a5.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a5.port_b_read_enable_clock = "clock1";
defparam ram_block2a5.ram_block_type = "auto";

endmodule
