// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition"

// DATE "04/09/2019 16:20:06"

// 
// Device: Altera 10AX016E3F27E1HG Package FBGA672
// 

// 
// This greybox netlist file is for third party Synthesis Tools
// for timing and resource estimation only.
// 


module dp_32bit (
	data,
	wraddress,
	rdaddress,
	wren,
	wrclock,
	rdclock,
	q)/* synthesis synthesis_greybox=0 */;
input 	[31:0] data;
input 	[11:0] wraddress;
input 	[11:0] rdaddress;
input 	wren;
input 	wrclock;
input 	rdclock;
output 	[31:0] q;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[0] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[1] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[2] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[3] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[4] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[5] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[6] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[7] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[8] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[9] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[10] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[11] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[12] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[13] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[14] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[15] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[16] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[17] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[18] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[19] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[20] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[21] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[22] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[23] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[24] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[25] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[26] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[27] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[28] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[29] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[30] ;
wire \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[31] ;
wire \wren~input_o ;
wire \wrclock~input_o ;
wire \rdclock~input_o ;
wire \data[0]~input_o ;
wire \wraddress[0]~input_o ;
wire \wraddress[1]~input_o ;
wire \wraddress[2]~input_o ;
wire \wraddress[3]~input_o ;
wire \wraddress[4]~input_o ;
wire \wraddress[5]~input_o ;
wire \wraddress[6]~input_o ;
wire \wraddress[7]~input_o ;
wire \wraddress[8]~input_o ;
wire \wraddress[9]~input_o ;
wire \wraddress[10]~input_o ;
wire \wraddress[11]~input_o ;
wire \rdaddress[0]~input_o ;
wire \rdaddress[1]~input_o ;
wire \rdaddress[2]~input_o ;
wire \rdaddress[3]~input_o ;
wire \rdaddress[4]~input_o ;
wire \rdaddress[5]~input_o ;
wire \rdaddress[6]~input_o ;
wire \rdaddress[7]~input_o ;
wire \rdaddress[8]~input_o ;
wire \rdaddress[9]~input_o ;
wire \rdaddress[10]~input_o ;
wire \rdaddress[11]~input_o ;
wire \data[1]~input_o ;
wire \data[2]~input_o ;
wire \data[3]~input_o ;
wire \data[4]~input_o ;
wire \data[5]~input_o ;
wire \data[6]~input_o ;
wire \data[7]~input_o ;
wire \data[8]~input_o ;
wire \data[9]~input_o ;
wire \data[10]~input_o ;
wire \data[11]~input_o ;
wire \data[12]~input_o ;
wire \data[13]~input_o ;
wire \data[14]~input_o ;
wire \data[15]~input_o ;
wire \data[16]~input_o ;
wire \data[17]~input_o ;
wire \data[18]~input_o ;
wire \data[19]~input_o ;
wire \data[20]~input_o ;
wire \data[21]~input_o ;
wire \data[22]~input_o ;
wire \data[23]~input_o ;
wire \data[24]~input_o ;
wire \data[25]~input_o ;
wire \data[26]~input_o ;
wire \data[27]~input_o ;
wire \data[28]~input_o ;
wire \data[29]~input_o ;
wire \data[30]~input_o ;
wire \data[31]~input_o ;


dp_32bit_dp_32bit_ram_2port_181_hrffwma ram_2port_0(
	.q_b_0(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[0] ),
	.q_b_1(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[1] ),
	.q_b_2(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[2] ),
	.q_b_3(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[3] ),
	.q_b_4(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[4] ),
	.q_b_5(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[5] ),
	.q_b_6(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[6] ),
	.q_b_7(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[7] ),
	.q_b_8(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[8] ),
	.q_b_9(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[9] ),
	.q_b_10(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[10] ),
	.q_b_11(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[11] ),
	.q_b_12(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[12] ),
	.q_b_13(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[13] ),
	.q_b_14(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[14] ),
	.q_b_15(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[15] ),
	.q_b_16(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[16] ),
	.q_b_17(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[17] ),
	.q_b_18(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[18] ),
	.q_b_19(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[19] ),
	.q_b_20(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[20] ),
	.q_b_21(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[21] ),
	.q_b_22(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[22] ),
	.q_b_23(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[23] ),
	.q_b_24(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[24] ),
	.q_b_25(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[25] ),
	.q_b_26(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[26] ),
	.q_b_27(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[27] ),
	.q_b_28(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[28] ),
	.q_b_29(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[29] ),
	.q_b_30(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[30] ),
	.q_b_31(\ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[31] ),
	.wren(\wren~input_o ),
	.wrclock(\wrclock~input_o ),
	.rdclock(\rdclock~input_o ),
	.data_0(\data[0]~input_o ),
	.wraddress_0(\wraddress[0]~input_o ),
	.wraddress_1(\wraddress[1]~input_o ),
	.wraddress_2(\wraddress[2]~input_o ),
	.wraddress_3(\wraddress[3]~input_o ),
	.wraddress_4(\wraddress[4]~input_o ),
	.wraddress_5(\wraddress[5]~input_o ),
	.wraddress_6(\wraddress[6]~input_o ),
	.wraddress_7(\wraddress[7]~input_o ),
	.wraddress_8(\wraddress[8]~input_o ),
	.wraddress_9(\wraddress[9]~input_o ),
	.wraddress_10(\wraddress[10]~input_o ),
	.wraddress_11(\wraddress[11]~input_o ),
	.rdaddress_0(\rdaddress[0]~input_o ),
	.rdaddress_1(\rdaddress[1]~input_o ),
	.rdaddress_2(\rdaddress[2]~input_o ),
	.rdaddress_3(\rdaddress[3]~input_o ),
	.rdaddress_4(\rdaddress[4]~input_o ),
	.rdaddress_5(\rdaddress[5]~input_o ),
	.rdaddress_6(\rdaddress[6]~input_o ),
	.rdaddress_7(\rdaddress[7]~input_o ),
	.rdaddress_8(\rdaddress[8]~input_o ),
	.rdaddress_9(\rdaddress[9]~input_o ),
	.rdaddress_10(\rdaddress[10]~input_o ),
	.rdaddress_11(\rdaddress[11]~input_o ),
	.data_1(\data[1]~input_o ),
	.data_2(\data[2]~input_o ),
	.data_3(\data[3]~input_o ),
	.data_4(\data[4]~input_o ),
	.data_5(\data[5]~input_o ),
	.data_6(\data[6]~input_o ),
	.data_7(\data[7]~input_o ),
	.data_8(\data[8]~input_o ),
	.data_9(\data[9]~input_o ),
	.data_10(\data[10]~input_o ),
	.data_11(\data[11]~input_o ),
	.data_12(\data[12]~input_o ),
	.data_13(\data[13]~input_o ),
	.data_14(\data[14]~input_o ),
	.data_15(\data[15]~input_o ),
	.data_16(\data[16]~input_o ),
	.data_17(\data[17]~input_o ),
	.data_18(\data[18]~input_o ),
	.data_19(\data[19]~input_o ),
	.data_20(\data[20]~input_o ),
	.data_21(\data[21]~input_o ),
	.data_22(\data[22]~input_o ),
	.data_23(\data[23]~input_o ),
	.data_24(\data[24]~input_o ),
	.data_25(\data[25]~input_o ),
	.data_26(\data[26]~input_o ),
	.data_27(\data[27]~input_o ),
	.data_28(\data[28]~input_o ),
	.data_29(\data[29]~input_o ),
	.data_30(\data[30]~input_o ),
	.data_31(\data[31]~input_o ));

assign \wren~input_o  = wren;

assign \wrclock~input_o  = wrclock;

assign \rdclock~input_o  = rdclock;

assign \data[0]~input_o  = data[0];

assign \wraddress[0]~input_o  = wraddress[0];

assign \wraddress[1]~input_o  = wraddress[1];

assign \wraddress[2]~input_o  = wraddress[2];

assign \wraddress[3]~input_o  = wraddress[3];

assign \wraddress[4]~input_o  = wraddress[4];

assign \wraddress[5]~input_o  = wraddress[5];

assign \wraddress[6]~input_o  = wraddress[6];

assign \wraddress[7]~input_o  = wraddress[7];

assign \wraddress[8]~input_o  = wraddress[8];

assign \wraddress[9]~input_o  = wraddress[9];

assign \wraddress[10]~input_o  = wraddress[10];

assign \wraddress[11]~input_o  = wraddress[11];

assign \rdaddress[0]~input_o  = rdaddress[0];

assign \rdaddress[1]~input_o  = rdaddress[1];

assign \rdaddress[2]~input_o  = rdaddress[2];

assign \rdaddress[3]~input_o  = rdaddress[3];

assign \rdaddress[4]~input_o  = rdaddress[4];

assign \rdaddress[5]~input_o  = rdaddress[5];

assign \rdaddress[6]~input_o  = rdaddress[6];

assign \rdaddress[7]~input_o  = rdaddress[7];

assign \rdaddress[8]~input_o  = rdaddress[8];

assign \rdaddress[9]~input_o  = rdaddress[9];

assign \rdaddress[10]~input_o  = rdaddress[10];

assign \rdaddress[11]~input_o  = rdaddress[11];

assign \data[1]~input_o  = data[1];

assign \data[2]~input_o  = data[2];

assign \data[3]~input_o  = data[3];

assign \data[4]~input_o  = data[4];

assign \data[5]~input_o  = data[5];

assign \data[6]~input_o  = data[6];

assign \data[7]~input_o  = data[7];

assign \data[8]~input_o  = data[8];

assign \data[9]~input_o  = data[9];

assign \data[10]~input_o  = data[10];

assign \data[11]~input_o  = data[11];

assign \data[12]~input_o  = data[12];

assign \data[13]~input_o  = data[13];

assign \data[14]~input_o  = data[14];

assign \data[15]~input_o  = data[15];

assign \data[16]~input_o  = data[16];

assign \data[17]~input_o  = data[17];

assign \data[18]~input_o  = data[18];

assign \data[19]~input_o  = data[19];

assign \data[20]~input_o  = data[20];

assign \data[21]~input_o  = data[21];

assign \data[22]~input_o  = data[22];

assign \data[23]~input_o  = data[23];

assign \data[24]~input_o  = data[24];

assign \data[25]~input_o  = data[25];

assign \data[26]~input_o  = data[26];

assign \data[27]~input_o  = data[27];

assign \data[28]~input_o  = data[28];

assign \data[29]~input_o  = data[29];

assign \data[30]~input_o  = data[30];

assign \data[31]~input_o  = data[31];

assign q[0] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[0] ;

assign q[1] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[1] ;

assign q[2] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[2] ;

assign q[3] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[3] ;

assign q[4] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[4] ;

assign q[5] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[5] ;

assign q[6] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[6] ;

assign q[7] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[7] ;

assign q[8] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[8] ;

assign q[9] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[9] ;

assign q[10] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[10] ;

assign q[11] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[11] ;

assign q[12] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[12] ;

assign q[13] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[13] ;

assign q[14] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[14] ;

assign q[15] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[15] ;

assign q[16] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[16] ;

assign q[17] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[17] ;

assign q[18] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[18] ;

assign q[19] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[19] ;

assign q[20] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[20] ;

assign q[21] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[21] ;

assign q[22] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[22] ;

assign q[23] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[23] ;

assign q[24] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[24] ;

assign q[25] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[25] ;

assign q[26] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[26] ;

assign q[27] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[27] ;

assign q[28] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[28] ;

assign q[29] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[29] ;

assign q[30] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[30] ;

assign q[31] = \ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|q_b[31] ;

endmodule

module dp_32bit_dp_32bit_ram_2port_181_hrffwma (
	q_b_0,
	q_b_1,
	q_b_2,
	q_b_3,
	q_b_4,
	q_b_5,
	q_b_6,
	q_b_7,
	q_b_8,
	q_b_9,
	q_b_10,
	q_b_11,
	q_b_12,
	q_b_13,
	q_b_14,
	q_b_15,
	q_b_16,
	q_b_17,
	q_b_18,
	q_b_19,
	q_b_20,
	q_b_21,
	q_b_22,
	q_b_23,
	q_b_24,
	q_b_25,
	q_b_26,
	q_b_27,
	q_b_28,
	q_b_29,
	q_b_30,
	q_b_31,
	wren,
	wrclock,
	rdclock,
	data_0,
	wraddress_0,
	wraddress_1,
	wraddress_2,
	wraddress_3,
	wraddress_4,
	wraddress_5,
	wraddress_6,
	wraddress_7,
	wraddress_8,
	wraddress_9,
	wraddress_10,
	wraddress_11,
	rdaddress_0,
	rdaddress_1,
	rdaddress_2,
	rdaddress_3,
	rdaddress_4,
	rdaddress_5,
	rdaddress_6,
	rdaddress_7,
	rdaddress_8,
	rdaddress_9,
	rdaddress_10,
	rdaddress_11,
	data_1,
	data_2,
	data_3,
	data_4,
	data_5,
	data_6,
	data_7,
	data_8,
	data_9,
	data_10,
	data_11,
	data_12,
	data_13,
	data_14,
	data_15,
	data_16,
	data_17,
	data_18,
	data_19,
	data_20,
	data_21,
	data_22,
	data_23,
	data_24,
	data_25,
	data_26,
	data_27,
	data_28,
	data_29,
	data_30,
	data_31)/* synthesis synthesis_greybox=0 */;
output 	q_b_0;
output 	q_b_1;
output 	q_b_2;
output 	q_b_3;
output 	q_b_4;
output 	q_b_5;
output 	q_b_6;
output 	q_b_7;
output 	q_b_8;
output 	q_b_9;
output 	q_b_10;
output 	q_b_11;
output 	q_b_12;
output 	q_b_13;
output 	q_b_14;
output 	q_b_15;
output 	q_b_16;
output 	q_b_17;
output 	q_b_18;
output 	q_b_19;
output 	q_b_20;
output 	q_b_21;
output 	q_b_22;
output 	q_b_23;
output 	q_b_24;
output 	q_b_25;
output 	q_b_26;
output 	q_b_27;
output 	q_b_28;
output 	q_b_29;
output 	q_b_30;
output 	q_b_31;
input 	wren;
input 	wrclock;
input 	rdclock;
input 	data_0;
input 	wraddress_0;
input 	wraddress_1;
input 	wraddress_2;
input 	wraddress_3;
input 	wraddress_4;
input 	wraddress_5;
input 	wraddress_6;
input 	wraddress_7;
input 	wraddress_8;
input 	wraddress_9;
input 	wraddress_10;
input 	wraddress_11;
input 	rdaddress_0;
input 	rdaddress_1;
input 	rdaddress_2;
input 	rdaddress_3;
input 	rdaddress_4;
input 	rdaddress_5;
input 	rdaddress_6;
input 	rdaddress_7;
input 	rdaddress_8;
input 	rdaddress_9;
input 	rdaddress_10;
input 	rdaddress_11;
input 	data_1;
input 	data_2;
input 	data_3;
input 	data_4;
input 	data_5;
input 	data_6;
input 	data_7;
input 	data_8;
input 	data_9;
input 	data_10;
input 	data_11;
input 	data_12;
input 	data_13;
input 	data_14;
input 	data_15;
input 	data_16;
input 	data_17;
input 	data_18;
input 	data_19;
input 	data_20;
input 	data_21;
input 	data_22;
input 	data_23;
input 	data_24;
input 	data_25;
input 	data_26;
input 	data_27;
input 	data_28;
input 	data_29;
input 	data_30;
input 	data_31;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



dp_32bit_altera_syncram altera_syncram_component(
	.q_b({q_b_31,q_b_30,q_b_29,q_b_28,q_b_27,q_b_26,q_b_25,q_b_24,q_b_23,q_b_22,q_b_21,q_b_20,q_b_19,q_b_18,q_b_17,q_b_16,q_b_15,q_b_14,q_b_13,q_b_12,q_b_11,q_b_10,q_b_9,q_b_8,q_b_7,q_b_6,q_b_5,q_b_4,q_b_3,q_b_2,q_b_1,q_b_0}),
	.wren_a(wren),
	.clock0(wrclock),
	.clock1(rdclock),
	.data_a({data_31,data_30,data_29,data_28,data_27,data_26,data_25,data_24,data_23,data_22,data_21,data_20,data_19,data_18,data_17,data_16,data_15,data_14,data_13,data_12,data_11,data_10,data_9,data_8,data_7,data_6,data_5,data_4,data_3,data_2,data_1,data_0}),
	.address_a({wraddress_11,wraddress_10,wraddress_9,wraddress_8,wraddress_7,wraddress_6,wraddress_5,wraddress_4,wraddress_3,wraddress_2,wraddress_1,wraddress_0}),
	.address_b({rdaddress_11,rdaddress_10,rdaddress_9,rdaddress_8,rdaddress_7,rdaddress_6,rdaddress_5,rdaddress_4,rdaddress_3,rdaddress_2,rdaddress_1,rdaddress_0}));

endmodule

module dp_32bit_altera_syncram (
	q_b,
	wren_a,
	clock0,
	clock1,
	data_a,
	address_a,
	address_b)/* synthesis synthesis_greybox=0 */;
output 	[31:0] q_b;
input 	wren_a;
input 	clock0;
input 	clock1;
input 	[31:0] data_a;
input 	[11:0] address_a;
input 	[11:0] address_b;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



dp_32bit_altera_syncram_l4s1 auto_generated(
	.q_b({q_b[31],q_b[30],q_b[29],q_b[28],q_b[27],q_b[26],q_b[25],q_b[24],q_b[23],q_b[22],q_b[21],q_b[20],q_b[19],q_b[18],q_b[17],q_b[16],q_b[15],q_b[14],q_b[13],q_b[12],q_b[11],q_b[10],q_b[9],q_b[8],q_b[7],q_b[6],q_b[5],q_b[4],q_b[3],q_b[2],q_b[1],q_b[0]}),
	.wren_a(wren_a),
	.clock0(clock0),
	.clock1(clock1),
	.data_a({data_a[31],data_a[30],data_a[29],data_a[28],data_a[27],data_a[26],data_a[25],data_a[24],data_a[23],data_a[22],data_a[21],data_a[20],data_a[19],data_a[18],data_a[17],data_a[16],data_a[15],data_a[14],data_a[13],data_a[12],data_a[11],data_a[10],data_a[9],data_a[8],data_a[7],data_a[6],data_a[5],data_a[4],data_a[3],data_a[2],data_a[1],data_a[0]}),
	.address_a({address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.address_b({address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}));

endmodule

module dp_32bit_altera_syncram_l4s1 (
	q_b,
	wren_a,
	clock0,
	clock1,
	data_a,
	address_a,
	address_b)/* synthesis synthesis_greybox=0 */;
output 	[31:0] q_b;
input 	wren_a;
input 	clock0;
input 	clock1;
input 	[31:0] data_a;
input 	[11:0] address_a;
input 	[11:0] address_b;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



dp_32bit_altsyncram_hj84 altsyncram1(
	.q_b({q_b[31],q_b[30],q_b[29],q_b[28],q_b[27],q_b[26],q_b[25],q_b[24],q_b[23],q_b[22],q_b[21],q_b[20],q_b[19],q_b[18],q_b[17],q_b[16],q_b[15],q_b[14],q_b[13],q_b[12],q_b[11],q_b[10],q_b[9],q_b[8],q_b[7],q_b[6],q_b[5],q_b[4],q_b[3],q_b[2],q_b[1],q_b[0]}),
	.wren_a(wren_a),
	.clock0(clock0),
	.clock1(clock1),
	.data_a({data_a[31],data_a[30],data_a[29],data_a[28],data_a[27],data_a[26],data_a[25],data_a[24],data_a[23],data_a[22],data_a[21],data_a[20],data_a[19],data_a[18],data_a[17],data_a[16],data_a[15],data_a[14],data_a[13],data_a[12],data_a[11],data_a[10],data_a[9],data_a[8],data_a[7],data_a[6],data_a[5],data_a[4],data_a[3],data_a[2],data_a[1],data_a[0]}),
	.address_a({address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.address_b({address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}));

endmodule

module dp_32bit_altsyncram_hj84 (
	q_b,
	wren_a,
	clock0,
	clock1,
	data_a,
	address_a,
	address_b)/* synthesis synthesis_greybox=0 */;
output 	[31:0] q_b;
input 	wren_a;
input 	clock0;
input 	clock1;
input 	[31:0] data_a;
input 	[11:0] address_a;
input 	[11:0] address_b;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;


wire [143:0] ram_block2a0_PORTBDATAOUT_bus;
wire [143:0] ram_block2a1_PORTBDATAOUT_bus;
wire [143:0] ram_block2a2_PORTBDATAOUT_bus;
wire [143:0] ram_block2a3_PORTBDATAOUT_bus;
wire [143:0] ram_block2a4_PORTBDATAOUT_bus;
wire [143:0] ram_block2a5_PORTBDATAOUT_bus;
wire [143:0] ram_block2a6_PORTBDATAOUT_bus;
wire [143:0] ram_block2a7_PORTBDATAOUT_bus;
wire [143:0] ram_block2a8_PORTBDATAOUT_bus;
wire [143:0] ram_block2a9_PORTBDATAOUT_bus;
wire [143:0] ram_block2a10_PORTBDATAOUT_bus;
wire [143:0] ram_block2a11_PORTBDATAOUT_bus;
wire [143:0] ram_block2a12_PORTBDATAOUT_bus;
wire [143:0] ram_block2a13_PORTBDATAOUT_bus;
wire [143:0] ram_block2a14_PORTBDATAOUT_bus;
wire [143:0] ram_block2a15_PORTBDATAOUT_bus;
wire [143:0] ram_block2a16_PORTBDATAOUT_bus;
wire [143:0] ram_block2a17_PORTBDATAOUT_bus;
wire [143:0] ram_block2a18_PORTBDATAOUT_bus;
wire [143:0] ram_block2a19_PORTBDATAOUT_bus;
wire [143:0] ram_block2a20_PORTBDATAOUT_bus;
wire [143:0] ram_block2a21_PORTBDATAOUT_bus;
wire [143:0] ram_block2a22_PORTBDATAOUT_bus;
wire [143:0] ram_block2a23_PORTBDATAOUT_bus;
wire [143:0] ram_block2a24_PORTBDATAOUT_bus;
wire [143:0] ram_block2a25_PORTBDATAOUT_bus;
wire [143:0] ram_block2a26_PORTBDATAOUT_bus;
wire [143:0] ram_block2a27_PORTBDATAOUT_bus;
wire [143:0] ram_block2a28_PORTBDATAOUT_bus;
wire [143:0] ram_block2a29_PORTBDATAOUT_bus;
wire [143:0] ram_block2a30_PORTBDATAOUT_bus;
wire [143:0] ram_block2a31_PORTBDATAOUT_bus;

assign q_b[0] = ram_block2a0_PORTBDATAOUT_bus[0];

assign q_b[1] = ram_block2a1_PORTBDATAOUT_bus[0];

assign q_b[2] = ram_block2a2_PORTBDATAOUT_bus[0];

assign q_b[3] = ram_block2a3_PORTBDATAOUT_bus[0];

assign q_b[4] = ram_block2a4_PORTBDATAOUT_bus[0];

assign q_b[5] = ram_block2a5_PORTBDATAOUT_bus[0];

assign q_b[6] = ram_block2a6_PORTBDATAOUT_bus[0];

assign q_b[7] = ram_block2a7_PORTBDATAOUT_bus[0];

assign q_b[8] = ram_block2a8_PORTBDATAOUT_bus[0];

assign q_b[9] = ram_block2a9_PORTBDATAOUT_bus[0];

assign q_b[10] = ram_block2a10_PORTBDATAOUT_bus[0];

assign q_b[11] = ram_block2a11_PORTBDATAOUT_bus[0];

assign q_b[12] = ram_block2a12_PORTBDATAOUT_bus[0];

assign q_b[13] = ram_block2a13_PORTBDATAOUT_bus[0];

assign q_b[14] = ram_block2a14_PORTBDATAOUT_bus[0];

assign q_b[15] = ram_block2a15_PORTBDATAOUT_bus[0];

assign q_b[16] = ram_block2a16_PORTBDATAOUT_bus[0];

assign q_b[17] = ram_block2a17_PORTBDATAOUT_bus[0];

assign q_b[18] = ram_block2a18_PORTBDATAOUT_bus[0];

assign q_b[19] = ram_block2a19_PORTBDATAOUT_bus[0];

assign q_b[20] = ram_block2a20_PORTBDATAOUT_bus[0];

assign q_b[21] = ram_block2a21_PORTBDATAOUT_bus[0];

assign q_b[22] = ram_block2a22_PORTBDATAOUT_bus[0];

assign q_b[23] = ram_block2a23_PORTBDATAOUT_bus[0];

assign q_b[24] = ram_block2a24_PORTBDATAOUT_bus[0];

assign q_b[25] = ram_block2a25_PORTBDATAOUT_bus[0];

assign q_b[26] = ram_block2a26_PORTBDATAOUT_bus[0];

assign q_b[27] = ram_block2a27_PORTBDATAOUT_bus[0];

assign q_b[28] = ram_block2a28_PORTBDATAOUT_bus[0];

assign q_b[29] = ram_block2a29_PORTBDATAOUT_bus[0];

assign q_b[30] = ram_block2a30_PORTBDATAOUT_bus[0];

assign q_b[31] = ram_block2a31_PORTBDATAOUT_bus[0];

twentynm_ram_block ram_block2a0(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[0]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a0_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a0.clk0_core_clock_enable = "ena0";
defparam ram_block2a0.data_interleave_offset_in_bits = 1;
defparam ram_block2a0.data_interleave_width_in_bits = 1;
defparam ram_block2a0.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a0.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a0.operation_mode = "dual_port";
defparam ram_block2a0.port_a_address_clear = "none";
defparam ram_block2a0.port_a_address_width = 12;
defparam ram_block2a0.port_a_data_out_clear = "none";
defparam ram_block2a0.port_a_data_out_clock = "none";
defparam ram_block2a0.port_a_data_width = 1;
defparam ram_block2a0.port_a_first_address = 0;
defparam ram_block2a0.port_a_first_bit_number = 0;
defparam ram_block2a0.port_a_last_address = 4095;
defparam ram_block2a0.port_a_logical_ram_depth = 4096;
defparam ram_block2a0.port_a_logical_ram_width = 32;
defparam ram_block2a0.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a0.port_b_address_clear = "none";
defparam ram_block2a0.port_b_address_clock = "clock1";
defparam ram_block2a0.port_b_address_width = 12;
defparam ram_block2a0.port_b_data_out_clear = "none";
defparam ram_block2a0.port_b_data_out_clock = "clock1";
defparam ram_block2a0.port_b_data_width = 1;
defparam ram_block2a0.port_b_first_address = 0;
defparam ram_block2a0.port_b_first_bit_number = 0;
defparam ram_block2a0.port_b_last_address = 4095;
defparam ram_block2a0.port_b_logical_ram_depth = 4096;
defparam ram_block2a0.port_b_logical_ram_width = 32;
defparam ram_block2a0.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a0.port_b_read_enable_clock = "clock1";
defparam ram_block2a0.ram_block_type = "auto";

twentynm_ram_block ram_block2a1(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[1]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a1_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a1.clk0_core_clock_enable = "ena0";
defparam ram_block2a1.data_interleave_offset_in_bits = 1;
defparam ram_block2a1.data_interleave_width_in_bits = 1;
defparam ram_block2a1.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a1.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a1.operation_mode = "dual_port";
defparam ram_block2a1.port_a_address_clear = "none";
defparam ram_block2a1.port_a_address_width = 12;
defparam ram_block2a1.port_a_data_out_clear = "none";
defparam ram_block2a1.port_a_data_out_clock = "none";
defparam ram_block2a1.port_a_data_width = 1;
defparam ram_block2a1.port_a_first_address = 0;
defparam ram_block2a1.port_a_first_bit_number = 1;
defparam ram_block2a1.port_a_last_address = 4095;
defparam ram_block2a1.port_a_logical_ram_depth = 4096;
defparam ram_block2a1.port_a_logical_ram_width = 32;
defparam ram_block2a1.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a1.port_b_address_clear = "none";
defparam ram_block2a1.port_b_address_clock = "clock1";
defparam ram_block2a1.port_b_address_width = 12;
defparam ram_block2a1.port_b_data_out_clear = "none";
defparam ram_block2a1.port_b_data_out_clock = "clock1";
defparam ram_block2a1.port_b_data_width = 1;
defparam ram_block2a1.port_b_first_address = 0;
defparam ram_block2a1.port_b_first_bit_number = 1;
defparam ram_block2a1.port_b_last_address = 4095;
defparam ram_block2a1.port_b_logical_ram_depth = 4096;
defparam ram_block2a1.port_b_logical_ram_width = 32;
defparam ram_block2a1.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a1.port_b_read_enable_clock = "clock1";
defparam ram_block2a1.ram_block_type = "auto";

twentynm_ram_block ram_block2a2(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[2]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a2_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a2.clk0_core_clock_enable = "ena0";
defparam ram_block2a2.data_interleave_offset_in_bits = 1;
defparam ram_block2a2.data_interleave_width_in_bits = 1;
defparam ram_block2a2.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a2.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a2.operation_mode = "dual_port";
defparam ram_block2a2.port_a_address_clear = "none";
defparam ram_block2a2.port_a_address_width = 12;
defparam ram_block2a2.port_a_data_out_clear = "none";
defparam ram_block2a2.port_a_data_out_clock = "none";
defparam ram_block2a2.port_a_data_width = 1;
defparam ram_block2a2.port_a_first_address = 0;
defparam ram_block2a2.port_a_first_bit_number = 2;
defparam ram_block2a2.port_a_last_address = 4095;
defparam ram_block2a2.port_a_logical_ram_depth = 4096;
defparam ram_block2a2.port_a_logical_ram_width = 32;
defparam ram_block2a2.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a2.port_b_address_clear = "none";
defparam ram_block2a2.port_b_address_clock = "clock1";
defparam ram_block2a2.port_b_address_width = 12;
defparam ram_block2a2.port_b_data_out_clear = "none";
defparam ram_block2a2.port_b_data_out_clock = "clock1";
defparam ram_block2a2.port_b_data_width = 1;
defparam ram_block2a2.port_b_first_address = 0;
defparam ram_block2a2.port_b_first_bit_number = 2;
defparam ram_block2a2.port_b_last_address = 4095;
defparam ram_block2a2.port_b_logical_ram_depth = 4096;
defparam ram_block2a2.port_b_logical_ram_width = 32;
defparam ram_block2a2.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a2.port_b_read_enable_clock = "clock1";
defparam ram_block2a2.ram_block_type = "auto";

twentynm_ram_block ram_block2a3(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[3]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a3_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a3.clk0_core_clock_enable = "ena0";
defparam ram_block2a3.data_interleave_offset_in_bits = 1;
defparam ram_block2a3.data_interleave_width_in_bits = 1;
defparam ram_block2a3.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a3.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a3.operation_mode = "dual_port";
defparam ram_block2a3.port_a_address_clear = "none";
defparam ram_block2a3.port_a_address_width = 12;
defparam ram_block2a3.port_a_data_out_clear = "none";
defparam ram_block2a3.port_a_data_out_clock = "none";
defparam ram_block2a3.port_a_data_width = 1;
defparam ram_block2a3.port_a_first_address = 0;
defparam ram_block2a3.port_a_first_bit_number = 3;
defparam ram_block2a3.port_a_last_address = 4095;
defparam ram_block2a3.port_a_logical_ram_depth = 4096;
defparam ram_block2a3.port_a_logical_ram_width = 32;
defparam ram_block2a3.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a3.port_b_address_clear = "none";
defparam ram_block2a3.port_b_address_clock = "clock1";
defparam ram_block2a3.port_b_address_width = 12;
defparam ram_block2a3.port_b_data_out_clear = "none";
defparam ram_block2a3.port_b_data_out_clock = "clock1";
defparam ram_block2a3.port_b_data_width = 1;
defparam ram_block2a3.port_b_first_address = 0;
defparam ram_block2a3.port_b_first_bit_number = 3;
defparam ram_block2a3.port_b_last_address = 4095;
defparam ram_block2a3.port_b_logical_ram_depth = 4096;
defparam ram_block2a3.port_b_logical_ram_width = 32;
defparam ram_block2a3.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a3.port_b_read_enable_clock = "clock1";
defparam ram_block2a3.ram_block_type = "auto";

twentynm_ram_block ram_block2a4(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[4]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a4_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a4.clk0_core_clock_enable = "ena0";
defparam ram_block2a4.data_interleave_offset_in_bits = 1;
defparam ram_block2a4.data_interleave_width_in_bits = 1;
defparam ram_block2a4.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a4.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a4.operation_mode = "dual_port";
defparam ram_block2a4.port_a_address_clear = "none";
defparam ram_block2a4.port_a_address_width = 12;
defparam ram_block2a4.port_a_data_out_clear = "none";
defparam ram_block2a4.port_a_data_out_clock = "none";
defparam ram_block2a4.port_a_data_width = 1;
defparam ram_block2a4.port_a_first_address = 0;
defparam ram_block2a4.port_a_first_bit_number = 4;
defparam ram_block2a4.port_a_last_address = 4095;
defparam ram_block2a4.port_a_logical_ram_depth = 4096;
defparam ram_block2a4.port_a_logical_ram_width = 32;
defparam ram_block2a4.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a4.port_b_address_clear = "none";
defparam ram_block2a4.port_b_address_clock = "clock1";
defparam ram_block2a4.port_b_address_width = 12;
defparam ram_block2a4.port_b_data_out_clear = "none";
defparam ram_block2a4.port_b_data_out_clock = "clock1";
defparam ram_block2a4.port_b_data_width = 1;
defparam ram_block2a4.port_b_first_address = 0;
defparam ram_block2a4.port_b_first_bit_number = 4;
defparam ram_block2a4.port_b_last_address = 4095;
defparam ram_block2a4.port_b_logical_ram_depth = 4096;
defparam ram_block2a4.port_b_logical_ram_width = 32;
defparam ram_block2a4.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a4.port_b_read_enable_clock = "clock1";
defparam ram_block2a4.ram_block_type = "auto";

twentynm_ram_block ram_block2a5(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[5]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a5_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a5.clk0_core_clock_enable = "ena0";
defparam ram_block2a5.data_interleave_offset_in_bits = 1;
defparam ram_block2a5.data_interleave_width_in_bits = 1;
defparam ram_block2a5.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a5.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a5.operation_mode = "dual_port";
defparam ram_block2a5.port_a_address_clear = "none";
defparam ram_block2a5.port_a_address_width = 12;
defparam ram_block2a5.port_a_data_out_clear = "none";
defparam ram_block2a5.port_a_data_out_clock = "none";
defparam ram_block2a5.port_a_data_width = 1;
defparam ram_block2a5.port_a_first_address = 0;
defparam ram_block2a5.port_a_first_bit_number = 5;
defparam ram_block2a5.port_a_last_address = 4095;
defparam ram_block2a5.port_a_logical_ram_depth = 4096;
defparam ram_block2a5.port_a_logical_ram_width = 32;
defparam ram_block2a5.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a5.port_b_address_clear = "none";
defparam ram_block2a5.port_b_address_clock = "clock1";
defparam ram_block2a5.port_b_address_width = 12;
defparam ram_block2a5.port_b_data_out_clear = "none";
defparam ram_block2a5.port_b_data_out_clock = "clock1";
defparam ram_block2a5.port_b_data_width = 1;
defparam ram_block2a5.port_b_first_address = 0;
defparam ram_block2a5.port_b_first_bit_number = 5;
defparam ram_block2a5.port_b_last_address = 4095;
defparam ram_block2a5.port_b_logical_ram_depth = 4096;
defparam ram_block2a5.port_b_logical_ram_width = 32;
defparam ram_block2a5.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a5.port_b_read_enable_clock = "clock1";
defparam ram_block2a5.ram_block_type = "auto";

twentynm_ram_block ram_block2a6(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[6]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a6_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a6.clk0_core_clock_enable = "ena0";
defparam ram_block2a6.data_interleave_offset_in_bits = 1;
defparam ram_block2a6.data_interleave_width_in_bits = 1;
defparam ram_block2a6.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a6.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a6.operation_mode = "dual_port";
defparam ram_block2a6.port_a_address_clear = "none";
defparam ram_block2a6.port_a_address_width = 12;
defparam ram_block2a6.port_a_data_out_clear = "none";
defparam ram_block2a6.port_a_data_out_clock = "none";
defparam ram_block2a6.port_a_data_width = 1;
defparam ram_block2a6.port_a_first_address = 0;
defparam ram_block2a6.port_a_first_bit_number = 6;
defparam ram_block2a6.port_a_last_address = 4095;
defparam ram_block2a6.port_a_logical_ram_depth = 4096;
defparam ram_block2a6.port_a_logical_ram_width = 32;
defparam ram_block2a6.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a6.port_b_address_clear = "none";
defparam ram_block2a6.port_b_address_clock = "clock1";
defparam ram_block2a6.port_b_address_width = 12;
defparam ram_block2a6.port_b_data_out_clear = "none";
defparam ram_block2a6.port_b_data_out_clock = "clock1";
defparam ram_block2a6.port_b_data_width = 1;
defparam ram_block2a6.port_b_first_address = 0;
defparam ram_block2a6.port_b_first_bit_number = 6;
defparam ram_block2a6.port_b_last_address = 4095;
defparam ram_block2a6.port_b_logical_ram_depth = 4096;
defparam ram_block2a6.port_b_logical_ram_width = 32;
defparam ram_block2a6.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a6.port_b_read_enable_clock = "clock1";
defparam ram_block2a6.ram_block_type = "auto";

twentynm_ram_block ram_block2a7(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[7]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a7_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a7.clk0_core_clock_enable = "ena0";
defparam ram_block2a7.data_interleave_offset_in_bits = 1;
defparam ram_block2a7.data_interleave_width_in_bits = 1;
defparam ram_block2a7.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a7.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a7.operation_mode = "dual_port";
defparam ram_block2a7.port_a_address_clear = "none";
defparam ram_block2a7.port_a_address_width = 12;
defparam ram_block2a7.port_a_data_out_clear = "none";
defparam ram_block2a7.port_a_data_out_clock = "none";
defparam ram_block2a7.port_a_data_width = 1;
defparam ram_block2a7.port_a_first_address = 0;
defparam ram_block2a7.port_a_first_bit_number = 7;
defparam ram_block2a7.port_a_last_address = 4095;
defparam ram_block2a7.port_a_logical_ram_depth = 4096;
defparam ram_block2a7.port_a_logical_ram_width = 32;
defparam ram_block2a7.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a7.port_b_address_clear = "none";
defparam ram_block2a7.port_b_address_clock = "clock1";
defparam ram_block2a7.port_b_address_width = 12;
defparam ram_block2a7.port_b_data_out_clear = "none";
defparam ram_block2a7.port_b_data_out_clock = "clock1";
defparam ram_block2a7.port_b_data_width = 1;
defparam ram_block2a7.port_b_first_address = 0;
defparam ram_block2a7.port_b_first_bit_number = 7;
defparam ram_block2a7.port_b_last_address = 4095;
defparam ram_block2a7.port_b_logical_ram_depth = 4096;
defparam ram_block2a7.port_b_logical_ram_width = 32;
defparam ram_block2a7.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a7.port_b_read_enable_clock = "clock1";
defparam ram_block2a7.ram_block_type = "auto";

twentynm_ram_block ram_block2a8(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[8]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a8_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a8.clk0_core_clock_enable = "ena0";
defparam ram_block2a8.data_interleave_offset_in_bits = 1;
defparam ram_block2a8.data_interleave_width_in_bits = 1;
defparam ram_block2a8.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a8.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a8.operation_mode = "dual_port";
defparam ram_block2a8.port_a_address_clear = "none";
defparam ram_block2a8.port_a_address_width = 12;
defparam ram_block2a8.port_a_data_out_clear = "none";
defparam ram_block2a8.port_a_data_out_clock = "none";
defparam ram_block2a8.port_a_data_width = 1;
defparam ram_block2a8.port_a_first_address = 0;
defparam ram_block2a8.port_a_first_bit_number = 8;
defparam ram_block2a8.port_a_last_address = 4095;
defparam ram_block2a8.port_a_logical_ram_depth = 4096;
defparam ram_block2a8.port_a_logical_ram_width = 32;
defparam ram_block2a8.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a8.port_b_address_clear = "none";
defparam ram_block2a8.port_b_address_clock = "clock1";
defparam ram_block2a8.port_b_address_width = 12;
defparam ram_block2a8.port_b_data_out_clear = "none";
defparam ram_block2a8.port_b_data_out_clock = "clock1";
defparam ram_block2a8.port_b_data_width = 1;
defparam ram_block2a8.port_b_first_address = 0;
defparam ram_block2a8.port_b_first_bit_number = 8;
defparam ram_block2a8.port_b_last_address = 4095;
defparam ram_block2a8.port_b_logical_ram_depth = 4096;
defparam ram_block2a8.port_b_logical_ram_width = 32;
defparam ram_block2a8.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a8.port_b_read_enable_clock = "clock1";
defparam ram_block2a8.ram_block_type = "auto";

twentynm_ram_block ram_block2a9(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[9]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a9_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a9.clk0_core_clock_enable = "ena0";
defparam ram_block2a9.data_interleave_offset_in_bits = 1;
defparam ram_block2a9.data_interleave_width_in_bits = 1;
defparam ram_block2a9.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a9.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a9.operation_mode = "dual_port";
defparam ram_block2a9.port_a_address_clear = "none";
defparam ram_block2a9.port_a_address_width = 12;
defparam ram_block2a9.port_a_data_out_clear = "none";
defparam ram_block2a9.port_a_data_out_clock = "none";
defparam ram_block2a9.port_a_data_width = 1;
defparam ram_block2a9.port_a_first_address = 0;
defparam ram_block2a9.port_a_first_bit_number = 9;
defparam ram_block2a9.port_a_last_address = 4095;
defparam ram_block2a9.port_a_logical_ram_depth = 4096;
defparam ram_block2a9.port_a_logical_ram_width = 32;
defparam ram_block2a9.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a9.port_b_address_clear = "none";
defparam ram_block2a9.port_b_address_clock = "clock1";
defparam ram_block2a9.port_b_address_width = 12;
defparam ram_block2a9.port_b_data_out_clear = "none";
defparam ram_block2a9.port_b_data_out_clock = "clock1";
defparam ram_block2a9.port_b_data_width = 1;
defparam ram_block2a9.port_b_first_address = 0;
defparam ram_block2a9.port_b_first_bit_number = 9;
defparam ram_block2a9.port_b_last_address = 4095;
defparam ram_block2a9.port_b_logical_ram_depth = 4096;
defparam ram_block2a9.port_b_logical_ram_width = 32;
defparam ram_block2a9.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a9.port_b_read_enable_clock = "clock1";
defparam ram_block2a9.ram_block_type = "auto";

twentynm_ram_block ram_block2a10(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[10]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a10_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a10.clk0_core_clock_enable = "ena0";
defparam ram_block2a10.data_interleave_offset_in_bits = 1;
defparam ram_block2a10.data_interleave_width_in_bits = 1;
defparam ram_block2a10.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a10.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a10.operation_mode = "dual_port";
defparam ram_block2a10.port_a_address_clear = "none";
defparam ram_block2a10.port_a_address_width = 12;
defparam ram_block2a10.port_a_data_out_clear = "none";
defparam ram_block2a10.port_a_data_out_clock = "none";
defparam ram_block2a10.port_a_data_width = 1;
defparam ram_block2a10.port_a_first_address = 0;
defparam ram_block2a10.port_a_first_bit_number = 10;
defparam ram_block2a10.port_a_last_address = 4095;
defparam ram_block2a10.port_a_logical_ram_depth = 4096;
defparam ram_block2a10.port_a_logical_ram_width = 32;
defparam ram_block2a10.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a10.port_b_address_clear = "none";
defparam ram_block2a10.port_b_address_clock = "clock1";
defparam ram_block2a10.port_b_address_width = 12;
defparam ram_block2a10.port_b_data_out_clear = "none";
defparam ram_block2a10.port_b_data_out_clock = "clock1";
defparam ram_block2a10.port_b_data_width = 1;
defparam ram_block2a10.port_b_first_address = 0;
defparam ram_block2a10.port_b_first_bit_number = 10;
defparam ram_block2a10.port_b_last_address = 4095;
defparam ram_block2a10.port_b_logical_ram_depth = 4096;
defparam ram_block2a10.port_b_logical_ram_width = 32;
defparam ram_block2a10.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a10.port_b_read_enable_clock = "clock1";
defparam ram_block2a10.ram_block_type = "auto";

twentynm_ram_block ram_block2a11(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[11]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a11_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a11.clk0_core_clock_enable = "ena0";
defparam ram_block2a11.data_interleave_offset_in_bits = 1;
defparam ram_block2a11.data_interleave_width_in_bits = 1;
defparam ram_block2a11.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a11.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a11.operation_mode = "dual_port";
defparam ram_block2a11.port_a_address_clear = "none";
defparam ram_block2a11.port_a_address_width = 12;
defparam ram_block2a11.port_a_data_out_clear = "none";
defparam ram_block2a11.port_a_data_out_clock = "none";
defparam ram_block2a11.port_a_data_width = 1;
defparam ram_block2a11.port_a_first_address = 0;
defparam ram_block2a11.port_a_first_bit_number = 11;
defparam ram_block2a11.port_a_last_address = 4095;
defparam ram_block2a11.port_a_logical_ram_depth = 4096;
defparam ram_block2a11.port_a_logical_ram_width = 32;
defparam ram_block2a11.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a11.port_b_address_clear = "none";
defparam ram_block2a11.port_b_address_clock = "clock1";
defparam ram_block2a11.port_b_address_width = 12;
defparam ram_block2a11.port_b_data_out_clear = "none";
defparam ram_block2a11.port_b_data_out_clock = "clock1";
defparam ram_block2a11.port_b_data_width = 1;
defparam ram_block2a11.port_b_first_address = 0;
defparam ram_block2a11.port_b_first_bit_number = 11;
defparam ram_block2a11.port_b_last_address = 4095;
defparam ram_block2a11.port_b_logical_ram_depth = 4096;
defparam ram_block2a11.port_b_logical_ram_width = 32;
defparam ram_block2a11.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a11.port_b_read_enable_clock = "clock1";
defparam ram_block2a11.ram_block_type = "auto";

twentynm_ram_block ram_block2a12(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[12]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a12_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a12.clk0_core_clock_enable = "ena0";
defparam ram_block2a12.data_interleave_offset_in_bits = 1;
defparam ram_block2a12.data_interleave_width_in_bits = 1;
defparam ram_block2a12.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a12.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a12.operation_mode = "dual_port";
defparam ram_block2a12.port_a_address_clear = "none";
defparam ram_block2a12.port_a_address_width = 12;
defparam ram_block2a12.port_a_data_out_clear = "none";
defparam ram_block2a12.port_a_data_out_clock = "none";
defparam ram_block2a12.port_a_data_width = 1;
defparam ram_block2a12.port_a_first_address = 0;
defparam ram_block2a12.port_a_first_bit_number = 12;
defparam ram_block2a12.port_a_last_address = 4095;
defparam ram_block2a12.port_a_logical_ram_depth = 4096;
defparam ram_block2a12.port_a_logical_ram_width = 32;
defparam ram_block2a12.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a12.port_b_address_clear = "none";
defparam ram_block2a12.port_b_address_clock = "clock1";
defparam ram_block2a12.port_b_address_width = 12;
defparam ram_block2a12.port_b_data_out_clear = "none";
defparam ram_block2a12.port_b_data_out_clock = "clock1";
defparam ram_block2a12.port_b_data_width = 1;
defparam ram_block2a12.port_b_first_address = 0;
defparam ram_block2a12.port_b_first_bit_number = 12;
defparam ram_block2a12.port_b_last_address = 4095;
defparam ram_block2a12.port_b_logical_ram_depth = 4096;
defparam ram_block2a12.port_b_logical_ram_width = 32;
defparam ram_block2a12.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a12.port_b_read_enable_clock = "clock1";
defparam ram_block2a12.ram_block_type = "auto";

twentynm_ram_block ram_block2a13(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[13]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a13_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a13.clk0_core_clock_enable = "ena0";
defparam ram_block2a13.data_interleave_offset_in_bits = 1;
defparam ram_block2a13.data_interleave_width_in_bits = 1;
defparam ram_block2a13.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a13.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a13.operation_mode = "dual_port";
defparam ram_block2a13.port_a_address_clear = "none";
defparam ram_block2a13.port_a_address_width = 12;
defparam ram_block2a13.port_a_data_out_clear = "none";
defparam ram_block2a13.port_a_data_out_clock = "none";
defparam ram_block2a13.port_a_data_width = 1;
defparam ram_block2a13.port_a_first_address = 0;
defparam ram_block2a13.port_a_first_bit_number = 13;
defparam ram_block2a13.port_a_last_address = 4095;
defparam ram_block2a13.port_a_logical_ram_depth = 4096;
defparam ram_block2a13.port_a_logical_ram_width = 32;
defparam ram_block2a13.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a13.port_b_address_clear = "none";
defparam ram_block2a13.port_b_address_clock = "clock1";
defparam ram_block2a13.port_b_address_width = 12;
defparam ram_block2a13.port_b_data_out_clear = "none";
defparam ram_block2a13.port_b_data_out_clock = "clock1";
defparam ram_block2a13.port_b_data_width = 1;
defparam ram_block2a13.port_b_first_address = 0;
defparam ram_block2a13.port_b_first_bit_number = 13;
defparam ram_block2a13.port_b_last_address = 4095;
defparam ram_block2a13.port_b_logical_ram_depth = 4096;
defparam ram_block2a13.port_b_logical_ram_width = 32;
defparam ram_block2a13.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a13.port_b_read_enable_clock = "clock1";
defparam ram_block2a13.ram_block_type = "auto";

twentynm_ram_block ram_block2a14(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[14]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a14_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a14.clk0_core_clock_enable = "ena0";
defparam ram_block2a14.data_interleave_offset_in_bits = 1;
defparam ram_block2a14.data_interleave_width_in_bits = 1;
defparam ram_block2a14.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a14.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a14.operation_mode = "dual_port";
defparam ram_block2a14.port_a_address_clear = "none";
defparam ram_block2a14.port_a_address_width = 12;
defparam ram_block2a14.port_a_data_out_clear = "none";
defparam ram_block2a14.port_a_data_out_clock = "none";
defparam ram_block2a14.port_a_data_width = 1;
defparam ram_block2a14.port_a_first_address = 0;
defparam ram_block2a14.port_a_first_bit_number = 14;
defparam ram_block2a14.port_a_last_address = 4095;
defparam ram_block2a14.port_a_logical_ram_depth = 4096;
defparam ram_block2a14.port_a_logical_ram_width = 32;
defparam ram_block2a14.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a14.port_b_address_clear = "none";
defparam ram_block2a14.port_b_address_clock = "clock1";
defparam ram_block2a14.port_b_address_width = 12;
defparam ram_block2a14.port_b_data_out_clear = "none";
defparam ram_block2a14.port_b_data_out_clock = "clock1";
defparam ram_block2a14.port_b_data_width = 1;
defparam ram_block2a14.port_b_first_address = 0;
defparam ram_block2a14.port_b_first_bit_number = 14;
defparam ram_block2a14.port_b_last_address = 4095;
defparam ram_block2a14.port_b_logical_ram_depth = 4096;
defparam ram_block2a14.port_b_logical_ram_width = 32;
defparam ram_block2a14.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a14.port_b_read_enable_clock = "clock1";
defparam ram_block2a14.ram_block_type = "auto";

twentynm_ram_block ram_block2a15(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[15]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a15_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a15.clk0_core_clock_enable = "ena0";
defparam ram_block2a15.data_interleave_offset_in_bits = 1;
defparam ram_block2a15.data_interleave_width_in_bits = 1;
defparam ram_block2a15.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a15.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a15.operation_mode = "dual_port";
defparam ram_block2a15.port_a_address_clear = "none";
defparam ram_block2a15.port_a_address_width = 12;
defparam ram_block2a15.port_a_data_out_clear = "none";
defparam ram_block2a15.port_a_data_out_clock = "none";
defparam ram_block2a15.port_a_data_width = 1;
defparam ram_block2a15.port_a_first_address = 0;
defparam ram_block2a15.port_a_first_bit_number = 15;
defparam ram_block2a15.port_a_last_address = 4095;
defparam ram_block2a15.port_a_logical_ram_depth = 4096;
defparam ram_block2a15.port_a_logical_ram_width = 32;
defparam ram_block2a15.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a15.port_b_address_clear = "none";
defparam ram_block2a15.port_b_address_clock = "clock1";
defparam ram_block2a15.port_b_address_width = 12;
defparam ram_block2a15.port_b_data_out_clear = "none";
defparam ram_block2a15.port_b_data_out_clock = "clock1";
defparam ram_block2a15.port_b_data_width = 1;
defparam ram_block2a15.port_b_first_address = 0;
defparam ram_block2a15.port_b_first_bit_number = 15;
defparam ram_block2a15.port_b_last_address = 4095;
defparam ram_block2a15.port_b_logical_ram_depth = 4096;
defparam ram_block2a15.port_b_logical_ram_width = 32;
defparam ram_block2a15.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a15.port_b_read_enable_clock = "clock1";
defparam ram_block2a15.ram_block_type = "auto";

twentynm_ram_block ram_block2a16(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[16]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a16_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a16.clk0_core_clock_enable = "ena0";
defparam ram_block2a16.data_interleave_offset_in_bits = 1;
defparam ram_block2a16.data_interleave_width_in_bits = 1;
defparam ram_block2a16.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a16.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a16.operation_mode = "dual_port";
defparam ram_block2a16.port_a_address_clear = "none";
defparam ram_block2a16.port_a_address_width = 12;
defparam ram_block2a16.port_a_data_out_clear = "none";
defparam ram_block2a16.port_a_data_out_clock = "none";
defparam ram_block2a16.port_a_data_width = 1;
defparam ram_block2a16.port_a_first_address = 0;
defparam ram_block2a16.port_a_first_bit_number = 16;
defparam ram_block2a16.port_a_last_address = 4095;
defparam ram_block2a16.port_a_logical_ram_depth = 4096;
defparam ram_block2a16.port_a_logical_ram_width = 32;
defparam ram_block2a16.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a16.port_b_address_clear = "none";
defparam ram_block2a16.port_b_address_clock = "clock1";
defparam ram_block2a16.port_b_address_width = 12;
defparam ram_block2a16.port_b_data_out_clear = "none";
defparam ram_block2a16.port_b_data_out_clock = "clock1";
defparam ram_block2a16.port_b_data_width = 1;
defparam ram_block2a16.port_b_first_address = 0;
defparam ram_block2a16.port_b_first_bit_number = 16;
defparam ram_block2a16.port_b_last_address = 4095;
defparam ram_block2a16.port_b_logical_ram_depth = 4096;
defparam ram_block2a16.port_b_logical_ram_width = 32;
defparam ram_block2a16.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a16.port_b_read_enable_clock = "clock1";
defparam ram_block2a16.ram_block_type = "auto";

twentynm_ram_block ram_block2a17(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[17]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a17_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a17.clk0_core_clock_enable = "ena0";
defparam ram_block2a17.data_interleave_offset_in_bits = 1;
defparam ram_block2a17.data_interleave_width_in_bits = 1;
defparam ram_block2a17.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a17.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a17.operation_mode = "dual_port";
defparam ram_block2a17.port_a_address_clear = "none";
defparam ram_block2a17.port_a_address_width = 12;
defparam ram_block2a17.port_a_data_out_clear = "none";
defparam ram_block2a17.port_a_data_out_clock = "none";
defparam ram_block2a17.port_a_data_width = 1;
defparam ram_block2a17.port_a_first_address = 0;
defparam ram_block2a17.port_a_first_bit_number = 17;
defparam ram_block2a17.port_a_last_address = 4095;
defparam ram_block2a17.port_a_logical_ram_depth = 4096;
defparam ram_block2a17.port_a_logical_ram_width = 32;
defparam ram_block2a17.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a17.port_b_address_clear = "none";
defparam ram_block2a17.port_b_address_clock = "clock1";
defparam ram_block2a17.port_b_address_width = 12;
defparam ram_block2a17.port_b_data_out_clear = "none";
defparam ram_block2a17.port_b_data_out_clock = "clock1";
defparam ram_block2a17.port_b_data_width = 1;
defparam ram_block2a17.port_b_first_address = 0;
defparam ram_block2a17.port_b_first_bit_number = 17;
defparam ram_block2a17.port_b_last_address = 4095;
defparam ram_block2a17.port_b_logical_ram_depth = 4096;
defparam ram_block2a17.port_b_logical_ram_width = 32;
defparam ram_block2a17.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a17.port_b_read_enable_clock = "clock1";
defparam ram_block2a17.ram_block_type = "auto";

twentynm_ram_block ram_block2a18(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[18]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a18_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a18.clk0_core_clock_enable = "ena0";
defparam ram_block2a18.data_interleave_offset_in_bits = 1;
defparam ram_block2a18.data_interleave_width_in_bits = 1;
defparam ram_block2a18.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a18.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a18.operation_mode = "dual_port";
defparam ram_block2a18.port_a_address_clear = "none";
defparam ram_block2a18.port_a_address_width = 12;
defparam ram_block2a18.port_a_data_out_clear = "none";
defparam ram_block2a18.port_a_data_out_clock = "none";
defparam ram_block2a18.port_a_data_width = 1;
defparam ram_block2a18.port_a_first_address = 0;
defparam ram_block2a18.port_a_first_bit_number = 18;
defparam ram_block2a18.port_a_last_address = 4095;
defparam ram_block2a18.port_a_logical_ram_depth = 4096;
defparam ram_block2a18.port_a_logical_ram_width = 32;
defparam ram_block2a18.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a18.port_b_address_clear = "none";
defparam ram_block2a18.port_b_address_clock = "clock1";
defparam ram_block2a18.port_b_address_width = 12;
defparam ram_block2a18.port_b_data_out_clear = "none";
defparam ram_block2a18.port_b_data_out_clock = "clock1";
defparam ram_block2a18.port_b_data_width = 1;
defparam ram_block2a18.port_b_first_address = 0;
defparam ram_block2a18.port_b_first_bit_number = 18;
defparam ram_block2a18.port_b_last_address = 4095;
defparam ram_block2a18.port_b_logical_ram_depth = 4096;
defparam ram_block2a18.port_b_logical_ram_width = 32;
defparam ram_block2a18.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a18.port_b_read_enable_clock = "clock1";
defparam ram_block2a18.ram_block_type = "auto";

twentynm_ram_block ram_block2a19(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[19]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a19_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a19.clk0_core_clock_enable = "ena0";
defparam ram_block2a19.data_interleave_offset_in_bits = 1;
defparam ram_block2a19.data_interleave_width_in_bits = 1;
defparam ram_block2a19.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a19.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a19.operation_mode = "dual_port";
defparam ram_block2a19.port_a_address_clear = "none";
defparam ram_block2a19.port_a_address_width = 12;
defparam ram_block2a19.port_a_data_out_clear = "none";
defparam ram_block2a19.port_a_data_out_clock = "none";
defparam ram_block2a19.port_a_data_width = 1;
defparam ram_block2a19.port_a_first_address = 0;
defparam ram_block2a19.port_a_first_bit_number = 19;
defparam ram_block2a19.port_a_last_address = 4095;
defparam ram_block2a19.port_a_logical_ram_depth = 4096;
defparam ram_block2a19.port_a_logical_ram_width = 32;
defparam ram_block2a19.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a19.port_b_address_clear = "none";
defparam ram_block2a19.port_b_address_clock = "clock1";
defparam ram_block2a19.port_b_address_width = 12;
defparam ram_block2a19.port_b_data_out_clear = "none";
defparam ram_block2a19.port_b_data_out_clock = "clock1";
defparam ram_block2a19.port_b_data_width = 1;
defparam ram_block2a19.port_b_first_address = 0;
defparam ram_block2a19.port_b_first_bit_number = 19;
defparam ram_block2a19.port_b_last_address = 4095;
defparam ram_block2a19.port_b_logical_ram_depth = 4096;
defparam ram_block2a19.port_b_logical_ram_width = 32;
defparam ram_block2a19.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a19.port_b_read_enable_clock = "clock1";
defparam ram_block2a19.ram_block_type = "auto";

twentynm_ram_block ram_block2a20(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[20]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a20_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a20.clk0_core_clock_enable = "ena0";
defparam ram_block2a20.data_interleave_offset_in_bits = 1;
defparam ram_block2a20.data_interleave_width_in_bits = 1;
defparam ram_block2a20.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a20.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a20.operation_mode = "dual_port";
defparam ram_block2a20.port_a_address_clear = "none";
defparam ram_block2a20.port_a_address_width = 12;
defparam ram_block2a20.port_a_data_out_clear = "none";
defparam ram_block2a20.port_a_data_out_clock = "none";
defparam ram_block2a20.port_a_data_width = 1;
defparam ram_block2a20.port_a_first_address = 0;
defparam ram_block2a20.port_a_first_bit_number = 20;
defparam ram_block2a20.port_a_last_address = 4095;
defparam ram_block2a20.port_a_logical_ram_depth = 4096;
defparam ram_block2a20.port_a_logical_ram_width = 32;
defparam ram_block2a20.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a20.port_b_address_clear = "none";
defparam ram_block2a20.port_b_address_clock = "clock1";
defparam ram_block2a20.port_b_address_width = 12;
defparam ram_block2a20.port_b_data_out_clear = "none";
defparam ram_block2a20.port_b_data_out_clock = "clock1";
defparam ram_block2a20.port_b_data_width = 1;
defparam ram_block2a20.port_b_first_address = 0;
defparam ram_block2a20.port_b_first_bit_number = 20;
defparam ram_block2a20.port_b_last_address = 4095;
defparam ram_block2a20.port_b_logical_ram_depth = 4096;
defparam ram_block2a20.port_b_logical_ram_width = 32;
defparam ram_block2a20.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a20.port_b_read_enable_clock = "clock1";
defparam ram_block2a20.ram_block_type = "auto";

twentynm_ram_block ram_block2a21(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[21]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a21_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a21.clk0_core_clock_enable = "ena0";
defparam ram_block2a21.data_interleave_offset_in_bits = 1;
defparam ram_block2a21.data_interleave_width_in_bits = 1;
defparam ram_block2a21.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a21.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a21.operation_mode = "dual_port";
defparam ram_block2a21.port_a_address_clear = "none";
defparam ram_block2a21.port_a_address_width = 12;
defparam ram_block2a21.port_a_data_out_clear = "none";
defparam ram_block2a21.port_a_data_out_clock = "none";
defparam ram_block2a21.port_a_data_width = 1;
defparam ram_block2a21.port_a_first_address = 0;
defparam ram_block2a21.port_a_first_bit_number = 21;
defparam ram_block2a21.port_a_last_address = 4095;
defparam ram_block2a21.port_a_logical_ram_depth = 4096;
defparam ram_block2a21.port_a_logical_ram_width = 32;
defparam ram_block2a21.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a21.port_b_address_clear = "none";
defparam ram_block2a21.port_b_address_clock = "clock1";
defparam ram_block2a21.port_b_address_width = 12;
defparam ram_block2a21.port_b_data_out_clear = "none";
defparam ram_block2a21.port_b_data_out_clock = "clock1";
defparam ram_block2a21.port_b_data_width = 1;
defparam ram_block2a21.port_b_first_address = 0;
defparam ram_block2a21.port_b_first_bit_number = 21;
defparam ram_block2a21.port_b_last_address = 4095;
defparam ram_block2a21.port_b_logical_ram_depth = 4096;
defparam ram_block2a21.port_b_logical_ram_width = 32;
defparam ram_block2a21.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a21.port_b_read_enable_clock = "clock1";
defparam ram_block2a21.ram_block_type = "auto";

twentynm_ram_block ram_block2a22(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[22]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a22_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a22.clk0_core_clock_enable = "ena0";
defparam ram_block2a22.data_interleave_offset_in_bits = 1;
defparam ram_block2a22.data_interleave_width_in_bits = 1;
defparam ram_block2a22.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a22.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a22.operation_mode = "dual_port";
defparam ram_block2a22.port_a_address_clear = "none";
defparam ram_block2a22.port_a_address_width = 12;
defparam ram_block2a22.port_a_data_out_clear = "none";
defparam ram_block2a22.port_a_data_out_clock = "none";
defparam ram_block2a22.port_a_data_width = 1;
defparam ram_block2a22.port_a_first_address = 0;
defparam ram_block2a22.port_a_first_bit_number = 22;
defparam ram_block2a22.port_a_last_address = 4095;
defparam ram_block2a22.port_a_logical_ram_depth = 4096;
defparam ram_block2a22.port_a_logical_ram_width = 32;
defparam ram_block2a22.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a22.port_b_address_clear = "none";
defparam ram_block2a22.port_b_address_clock = "clock1";
defparam ram_block2a22.port_b_address_width = 12;
defparam ram_block2a22.port_b_data_out_clear = "none";
defparam ram_block2a22.port_b_data_out_clock = "clock1";
defparam ram_block2a22.port_b_data_width = 1;
defparam ram_block2a22.port_b_first_address = 0;
defparam ram_block2a22.port_b_first_bit_number = 22;
defparam ram_block2a22.port_b_last_address = 4095;
defparam ram_block2a22.port_b_logical_ram_depth = 4096;
defparam ram_block2a22.port_b_logical_ram_width = 32;
defparam ram_block2a22.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a22.port_b_read_enable_clock = "clock1";
defparam ram_block2a22.ram_block_type = "auto";

twentynm_ram_block ram_block2a23(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[23]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a23_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a23.clk0_core_clock_enable = "ena0";
defparam ram_block2a23.data_interleave_offset_in_bits = 1;
defparam ram_block2a23.data_interleave_width_in_bits = 1;
defparam ram_block2a23.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a23.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a23.operation_mode = "dual_port";
defparam ram_block2a23.port_a_address_clear = "none";
defparam ram_block2a23.port_a_address_width = 12;
defparam ram_block2a23.port_a_data_out_clear = "none";
defparam ram_block2a23.port_a_data_out_clock = "none";
defparam ram_block2a23.port_a_data_width = 1;
defparam ram_block2a23.port_a_first_address = 0;
defparam ram_block2a23.port_a_first_bit_number = 23;
defparam ram_block2a23.port_a_last_address = 4095;
defparam ram_block2a23.port_a_logical_ram_depth = 4096;
defparam ram_block2a23.port_a_logical_ram_width = 32;
defparam ram_block2a23.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a23.port_b_address_clear = "none";
defparam ram_block2a23.port_b_address_clock = "clock1";
defparam ram_block2a23.port_b_address_width = 12;
defparam ram_block2a23.port_b_data_out_clear = "none";
defparam ram_block2a23.port_b_data_out_clock = "clock1";
defparam ram_block2a23.port_b_data_width = 1;
defparam ram_block2a23.port_b_first_address = 0;
defparam ram_block2a23.port_b_first_bit_number = 23;
defparam ram_block2a23.port_b_last_address = 4095;
defparam ram_block2a23.port_b_logical_ram_depth = 4096;
defparam ram_block2a23.port_b_logical_ram_width = 32;
defparam ram_block2a23.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a23.port_b_read_enable_clock = "clock1";
defparam ram_block2a23.ram_block_type = "auto";

twentynm_ram_block ram_block2a24(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[24]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a24_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a24.clk0_core_clock_enable = "ena0";
defparam ram_block2a24.data_interleave_offset_in_bits = 1;
defparam ram_block2a24.data_interleave_width_in_bits = 1;
defparam ram_block2a24.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a24.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a24.operation_mode = "dual_port";
defparam ram_block2a24.port_a_address_clear = "none";
defparam ram_block2a24.port_a_address_width = 12;
defparam ram_block2a24.port_a_data_out_clear = "none";
defparam ram_block2a24.port_a_data_out_clock = "none";
defparam ram_block2a24.port_a_data_width = 1;
defparam ram_block2a24.port_a_first_address = 0;
defparam ram_block2a24.port_a_first_bit_number = 24;
defparam ram_block2a24.port_a_last_address = 4095;
defparam ram_block2a24.port_a_logical_ram_depth = 4096;
defparam ram_block2a24.port_a_logical_ram_width = 32;
defparam ram_block2a24.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a24.port_b_address_clear = "none";
defparam ram_block2a24.port_b_address_clock = "clock1";
defparam ram_block2a24.port_b_address_width = 12;
defparam ram_block2a24.port_b_data_out_clear = "none";
defparam ram_block2a24.port_b_data_out_clock = "clock1";
defparam ram_block2a24.port_b_data_width = 1;
defparam ram_block2a24.port_b_first_address = 0;
defparam ram_block2a24.port_b_first_bit_number = 24;
defparam ram_block2a24.port_b_last_address = 4095;
defparam ram_block2a24.port_b_logical_ram_depth = 4096;
defparam ram_block2a24.port_b_logical_ram_width = 32;
defparam ram_block2a24.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a24.port_b_read_enable_clock = "clock1";
defparam ram_block2a24.ram_block_type = "auto";

twentynm_ram_block ram_block2a25(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[25]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a25_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a25.clk0_core_clock_enable = "ena0";
defparam ram_block2a25.data_interleave_offset_in_bits = 1;
defparam ram_block2a25.data_interleave_width_in_bits = 1;
defparam ram_block2a25.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a25.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a25.operation_mode = "dual_port";
defparam ram_block2a25.port_a_address_clear = "none";
defparam ram_block2a25.port_a_address_width = 12;
defparam ram_block2a25.port_a_data_out_clear = "none";
defparam ram_block2a25.port_a_data_out_clock = "none";
defparam ram_block2a25.port_a_data_width = 1;
defparam ram_block2a25.port_a_first_address = 0;
defparam ram_block2a25.port_a_first_bit_number = 25;
defparam ram_block2a25.port_a_last_address = 4095;
defparam ram_block2a25.port_a_logical_ram_depth = 4096;
defparam ram_block2a25.port_a_logical_ram_width = 32;
defparam ram_block2a25.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a25.port_b_address_clear = "none";
defparam ram_block2a25.port_b_address_clock = "clock1";
defparam ram_block2a25.port_b_address_width = 12;
defparam ram_block2a25.port_b_data_out_clear = "none";
defparam ram_block2a25.port_b_data_out_clock = "clock1";
defparam ram_block2a25.port_b_data_width = 1;
defparam ram_block2a25.port_b_first_address = 0;
defparam ram_block2a25.port_b_first_bit_number = 25;
defparam ram_block2a25.port_b_last_address = 4095;
defparam ram_block2a25.port_b_logical_ram_depth = 4096;
defparam ram_block2a25.port_b_logical_ram_width = 32;
defparam ram_block2a25.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a25.port_b_read_enable_clock = "clock1";
defparam ram_block2a25.ram_block_type = "auto";

twentynm_ram_block ram_block2a26(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[26]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a26_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a26.clk0_core_clock_enable = "ena0";
defparam ram_block2a26.data_interleave_offset_in_bits = 1;
defparam ram_block2a26.data_interleave_width_in_bits = 1;
defparam ram_block2a26.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a26.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a26.operation_mode = "dual_port";
defparam ram_block2a26.port_a_address_clear = "none";
defparam ram_block2a26.port_a_address_width = 12;
defparam ram_block2a26.port_a_data_out_clear = "none";
defparam ram_block2a26.port_a_data_out_clock = "none";
defparam ram_block2a26.port_a_data_width = 1;
defparam ram_block2a26.port_a_first_address = 0;
defparam ram_block2a26.port_a_first_bit_number = 26;
defparam ram_block2a26.port_a_last_address = 4095;
defparam ram_block2a26.port_a_logical_ram_depth = 4096;
defparam ram_block2a26.port_a_logical_ram_width = 32;
defparam ram_block2a26.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a26.port_b_address_clear = "none";
defparam ram_block2a26.port_b_address_clock = "clock1";
defparam ram_block2a26.port_b_address_width = 12;
defparam ram_block2a26.port_b_data_out_clear = "none";
defparam ram_block2a26.port_b_data_out_clock = "clock1";
defparam ram_block2a26.port_b_data_width = 1;
defparam ram_block2a26.port_b_first_address = 0;
defparam ram_block2a26.port_b_first_bit_number = 26;
defparam ram_block2a26.port_b_last_address = 4095;
defparam ram_block2a26.port_b_logical_ram_depth = 4096;
defparam ram_block2a26.port_b_logical_ram_width = 32;
defparam ram_block2a26.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a26.port_b_read_enable_clock = "clock1";
defparam ram_block2a26.ram_block_type = "auto";

twentynm_ram_block ram_block2a27(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[27]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a27_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a27.clk0_core_clock_enable = "ena0";
defparam ram_block2a27.data_interleave_offset_in_bits = 1;
defparam ram_block2a27.data_interleave_width_in_bits = 1;
defparam ram_block2a27.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a27.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a27.operation_mode = "dual_port";
defparam ram_block2a27.port_a_address_clear = "none";
defparam ram_block2a27.port_a_address_width = 12;
defparam ram_block2a27.port_a_data_out_clear = "none";
defparam ram_block2a27.port_a_data_out_clock = "none";
defparam ram_block2a27.port_a_data_width = 1;
defparam ram_block2a27.port_a_first_address = 0;
defparam ram_block2a27.port_a_first_bit_number = 27;
defparam ram_block2a27.port_a_last_address = 4095;
defparam ram_block2a27.port_a_logical_ram_depth = 4096;
defparam ram_block2a27.port_a_logical_ram_width = 32;
defparam ram_block2a27.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a27.port_b_address_clear = "none";
defparam ram_block2a27.port_b_address_clock = "clock1";
defparam ram_block2a27.port_b_address_width = 12;
defparam ram_block2a27.port_b_data_out_clear = "none";
defparam ram_block2a27.port_b_data_out_clock = "clock1";
defparam ram_block2a27.port_b_data_width = 1;
defparam ram_block2a27.port_b_first_address = 0;
defparam ram_block2a27.port_b_first_bit_number = 27;
defparam ram_block2a27.port_b_last_address = 4095;
defparam ram_block2a27.port_b_logical_ram_depth = 4096;
defparam ram_block2a27.port_b_logical_ram_width = 32;
defparam ram_block2a27.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a27.port_b_read_enable_clock = "clock1";
defparam ram_block2a27.ram_block_type = "auto";

twentynm_ram_block ram_block2a28(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[28]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a28_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a28.clk0_core_clock_enable = "ena0";
defparam ram_block2a28.data_interleave_offset_in_bits = 1;
defparam ram_block2a28.data_interleave_width_in_bits = 1;
defparam ram_block2a28.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a28.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a28.operation_mode = "dual_port";
defparam ram_block2a28.port_a_address_clear = "none";
defparam ram_block2a28.port_a_address_width = 12;
defparam ram_block2a28.port_a_data_out_clear = "none";
defparam ram_block2a28.port_a_data_out_clock = "none";
defparam ram_block2a28.port_a_data_width = 1;
defparam ram_block2a28.port_a_first_address = 0;
defparam ram_block2a28.port_a_first_bit_number = 28;
defparam ram_block2a28.port_a_last_address = 4095;
defparam ram_block2a28.port_a_logical_ram_depth = 4096;
defparam ram_block2a28.port_a_logical_ram_width = 32;
defparam ram_block2a28.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a28.port_b_address_clear = "none";
defparam ram_block2a28.port_b_address_clock = "clock1";
defparam ram_block2a28.port_b_address_width = 12;
defparam ram_block2a28.port_b_data_out_clear = "none";
defparam ram_block2a28.port_b_data_out_clock = "clock1";
defparam ram_block2a28.port_b_data_width = 1;
defparam ram_block2a28.port_b_first_address = 0;
defparam ram_block2a28.port_b_first_bit_number = 28;
defparam ram_block2a28.port_b_last_address = 4095;
defparam ram_block2a28.port_b_logical_ram_depth = 4096;
defparam ram_block2a28.port_b_logical_ram_width = 32;
defparam ram_block2a28.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a28.port_b_read_enable_clock = "clock1";
defparam ram_block2a28.ram_block_type = "auto";

twentynm_ram_block ram_block2a29(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[29]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a29_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a29.clk0_core_clock_enable = "ena0";
defparam ram_block2a29.data_interleave_offset_in_bits = 1;
defparam ram_block2a29.data_interleave_width_in_bits = 1;
defparam ram_block2a29.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a29.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a29.operation_mode = "dual_port";
defparam ram_block2a29.port_a_address_clear = "none";
defparam ram_block2a29.port_a_address_width = 12;
defparam ram_block2a29.port_a_data_out_clear = "none";
defparam ram_block2a29.port_a_data_out_clock = "none";
defparam ram_block2a29.port_a_data_width = 1;
defparam ram_block2a29.port_a_first_address = 0;
defparam ram_block2a29.port_a_first_bit_number = 29;
defparam ram_block2a29.port_a_last_address = 4095;
defparam ram_block2a29.port_a_logical_ram_depth = 4096;
defparam ram_block2a29.port_a_logical_ram_width = 32;
defparam ram_block2a29.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a29.port_b_address_clear = "none";
defparam ram_block2a29.port_b_address_clock = "clock1";
defparam ram_block2a29.port_b_address_width = 12;
defparam ram_block2a29.port_b_data_out_clear = "none";
defparam ram_block2a29.port_b_data_out_clock = "clock1";
defparam ram_block2a29.port_b_data_width = 1;
defparam ram_block2a29.port_b_first_address = 0;
defparam ram_block2a29.port_b_first_bit_number = 29;
defparam ram_block2a29.port_b_last_address = 4095;
defparam ram_block2a29.port_b_logical_ram_depth = 4096;
defparam ram_block2a29.port_b_logical_ram_width = 32;
defparam ram_block2a29.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a29.port_b_read_enable_clock = "clock1";
defparam ram_block2a29.ram_block_type = "auto";

twentynm_ram_block ram_block2a30(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[30]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a30_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a30.clk0_core_clock_enable = "ena0";
defparam ram_block2a30.data_interleave_offset_in_bits = 1;
defparam ram_block2a30.data_interleave_width_in_bits = 1;
defparam ram_block2a30.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a30.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a30.operation_mode = "dual_port";
defparam ram_block2a30.port_a_address_clear = "none";
defparam ram_block2a30.port_a_address_width = 12;
defparam ram_block2a30.port_a_data_out_clear = "none";
defparam ram_block2a30.port_a_data_out_clock = "none";
defparam ram_block2a30.port_a_data_width = 1;
defparam ram_block2a30.port_a_first_address = 0;
defparam ram_block2a30.port_a_first_bit_number = 30;
defparam ram_block2a30.port_a_last_address = 4095;
defparam ram_block2a30.port_a_logical_ram_depth = 4096;
defparam ram_block2a30.port_a_logical_ram_width = 32;
defparam ram_block2a30.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a30.port_b_address_clear = "none";
defparam ram_block2a30.port_b_address_clock = "clock1";
defparam ram_block2a30.port_b_address_width = 12;
defparam ram_block2a30.port_b_data_out_clear = "none";
defparam ram_block2a30.port_b_data_out_clock = "clock1";
defparam ram_block2a30.port_b_data_width = 1;
defparam ram_block2a30.port_b_first_address = 0;
defparam ram_block2a30.port_b_first_bit_number = 30;
defparam ram_block2a30.port_b_last_address = 4095;
defparam ram_block2a30.port_b_logical_ram_depth = 4096;
defparam ram_block2a30.port_b_logical_ram_width = 32;
defparam ram_block2a30.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a30.port_b_read_enable_clock = "clock1";
defparam ram_block2a30.ram_block_type = "auto";

twentynm_ram_block ram_block2a31(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(gnd),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(vcc),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[31]}),
	.portaaddr({gnd,gnd,gnd,gnd,address_a[11],address_a[10],address_a[9],address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,address_b[11],address_b[10],address_b[9],address_b[8],address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block2a31_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block2a31.clk0_core_clock_enable = "ena0";
defparam ram_block2a31.data_interleave_offset_in_bits = 1;
defparam ram_block2a31.data_interleave_width_in_bits = 1;
defparam ram_block2a31.logical_ram_name = "dp_32bit_ram_2port_181_hrffwma:ram_2port_0|altera_syncram:altera_syncram_component|altera_syncram_l4s1:auto_generated|altsyncram_hj84:altsyncram1|ALTSYNCRAM";
defparam ram_block2a31.mixed_port_feed_through_mode = "dont_care";
defparam ram_block2a31.operation_mode = "dual_port";
defparam ram_block2a31.port_a_address_clear = "none";
defparam ram_block2a31.port_a_address_width = 12;
defparam ram_block2a31.port_a_data_out_clear = "none";
defparam ram_block2a31.port_a_data_out_clock = "none";
defparam ram_block2a31.port_a_data_width = 1;
defparam ram_block2a31.port_a_first_address = 0;
defparam ram_block2a31.port_a_first_bit_number = 31;
defparam ram_block2a31.port_a_last_address = 4095;
defparam ram_block2a31.port_a_logical_ram_depth = 4096;
defparam ram_block2a31.port_a_logical_ram_width = 32;
defparam ram_block2a31.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a31.port_b_address_clear = "none";
defparam ram_block2a31.port_b_address_clock = "clock1";
defparam ram_block2a31.port_b_address_width = 12;
defparam ram_block2a31.port_b_data_out_clear = "none";
defparam ram_block2a31.port_b_data_out_clock = "clock1";
defparam ram_block2a31.port_b_data_width = 1;
defparam ram_block2a31.port_b_first_address = 0;
defparam ram_block2a31.port_b_first_bit_number = 31;
defparam ram_block2a31.port_b_last_address = 4095;
defparam ram_block2a31.port_b_logical_ram_depth = 4096;
defparam ram_block2a31.port_b_logical_ram_width = 32;
defparam ram_block2a31.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block2a31.port_b_read_enable_clock = "clock1";
defparam ram_block2a31.ram_block_type = "auto";

endmodule
