// Copyright (C) 2018  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition"

// DATE "03/29/2019 13:35:16"

// 
// Device: Altera 10AX016E3F27E1HG Package FBGA672
// 

// 
// This greybox netlist file is for third party Synthesis Tools
// for timing and resource estimation only.
// 


module cntrl_fifo (
	data,
	wrreq,
	rdreq,
	wrclk,
	rdclk,
	q,
	rdempty,
	wrfull)/* synthesis synthesis_greybox=0 */;
input 	data;
input 	wrreq;
input 	rdreq;
input 	wrclk;
input 	rdclk;
output 	q;
output 	rdempty;
output 	wrfull;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[0] ;
wire \fifo_0|dcfifo_component|auto_generated|int_rdempty~combout ;
wire \fifo_0|dcfifo_component|auto_generated|int_wrfull~combout ;
wire \wrreq~input_o ;
wire \rdreq~input_o ;
wire \wrclk~input_o ;
wire \rdclk~input_o ;
wire \data~input_o ;


cntrl_fifo_cntrl_fifo_fifo_181_gccfdha fifo_0(
	.q_b_0(\fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[0] ),
	.int_rdempty(\fifo_0|dcfifo_component|auto_generated|int_rdempty~combout ),
	.int_wrfull(\fifo_0|dcfifo_component|auto_generated|int_wrfull~combout ),
	.wrreq(\wrreq~input_o ),
	.rdreq(\rdreq~input_o ),
	.wrclk(\wrclk~input_o ),
	.rdclk(\rdclk~input_o ),
	.data(\data~input_o ));

assign \wrreq~input_o  = wrreq;

assign \rdreq~input_o  = rdreq;

assign \wrclk~input_o  = wrclk;

assign \rdclk~input_o  = rdclk;

assign \data~input_o  = data;

assign q = \fifo_0|dcfifo_component|auto_generated|fifo_ram|q_b[0] ;

assign rdempty = \fifo_0|dcfifo_component|auto_generated|int_rdempty~combout ;

assign wrfull = \fifo_0|dcfifo_component|auto_generated|int_wrfull~combout ;

endmodule

module cntrl_fifo_cntrl_fifo_fifo_181_gccfdha (
	q_b_0,
	int_rdempty,
	int_wrfull,
	wrreq,
	rdreq,
	wrclk,
	rdclk,
	data)/* synthesis synthesis_greybox=0 */;
output 	q_b_0;
output 	int_rdempty;
output 	int_wrfull;
input 	wrreq;
input 	rdreq;
input 	wrclk;
input 	rdclk;
input 	data;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



cntrl_fifo_dcfifo_1 dcfifo_component(
	.q({q_b_0}),
	.int_rdempty(int_rdempty),
	.int_wrfull(int_wrfull),
	.wrreq(wrreq),
	.rdreq(rdreq),
	.wrclk(wrclk),
	.rdclk(rdclk),
	.data({data}));

endmodule

module cntrl_fifo_dcfifo_1 (
	q,
	int_rdempty,
	int_wrfull,
	wrreq,
	rdreq,
	wrclk,
	rdclk,
	data)/* synthesis synthesis_greybox=0 */;
output 	[0:0] q;
output 	int_rdempty;
output 	int_wrfull;
input 	wrreq;
input 	rdreq;
input 	wrclk;
input 	rdclk;
input 	[0:0] data;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



cntrl_fifo_dcfifo_t412 auto_generated(
	.q({q[0]}),
	.int_rdempty1(int_rdempty),
	.int_wrfull1(int_wrfull),
	.wrreq(wrreq),
	.rdreq(rdreq),
	.wrclk(wrclk),
	.rdclk(rdclk),
	.data({data[0]}));

endmodule

module cntrl_fifo_dcfifo_t412 (
	q,
	int_rdempty1,
	int_wrfull1,
	wrreq,
	rdreq,
	wrclk,
	rdclk,
	data)/* synthesis synthesis_greybox=0 */;
output 	[0:0] q;
output 	int_rdempty1;
output 	int_wrfull1;
input 	wrreq;
input 	rdreq;
input 	wrclk;
input 	rdclk;
input 	[0:0] data;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \valid_wrreq~0_combout ;
wire \valid_rdreq~0_combout ;
wire \wrptr_g[0]~q ;
wire \wrptr_g[1]~q ;
wire \wrptr_g[2]~q ;
wire \wrptr_g[3]~q ;
wire \wrptr_g[4]~q ;
wire \wrptr_g[5]~q ;
wire \wrptr_g[6]~q ;
wire \wrptr_g[8]~q ;
wire \wrptr_g[7]~q ;
wire \ram_address_a[7]~combout ;
wire \rdptr_g1p|counter1a0~q ;
wire \rdptr_g1p|counter1a1~q ;
wire \rdptr_g1p|counter1a2~q ;
wire \rdptr_g1p|counter1a3~q ;
wire \rdptr_g1p|counter1a4~q ;
wire \rdptr_g1p|counter1a5~q ;
wire \rdptr_g1p|counter1a6~q ;
wire \rdptr_g1p|counter1a7~q ;
wire \rdptr_g1p|counter1a8~q ;
wire \rdptr_g1p|_~0_combout ;
wire \rs_dgwp|dffpipe8|dffe10a[4]~q ;
wire \rs_dgwp|dffpipe8|dffe10a[2]~q ;
wire \rs_dgwp|dffpipe8|dffe10a[3]~q ;
wire \rs_dgwp|dffpipe8|dffe10a[0]~q ;
wire \rs_dgwp|dffpipe8|dffe10a[1]~q ;
wire \rdptr_g[4]~q ;
wire \rdptr_g[2]~q ;
wire \rdptr_g[3]~q ;
wire \rdptr_g[0]~q ;
wire \rdptr_g[1]~q ;
wire \rdemp_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~4_combout ;
wire \rs_dgwp|dffpipe8|dffe10a[6]~q ;
wire \rdempty_eq_comp1_msb|data_wire[0]~0_combout ;
wire \rdptr_g[6]~q ;
wire \rdempty_eq_comp_msb|data_wire[0]~0_combout ;
wire \rs_dgwp|dffpipe8|dffe10a[7]~q ;
wire \rs_dgwp|dffpipe8|dffe10a[8]~q ;
wire \rs_dgwp|dffpipe8|dffe10a[5]~q ;
wire \rdptr_g[7]~q ;
wire \rdptr_g[8]~q ;
wire \rdptr_g[5]~q ;
wire \rdemp_eq_comp_msb_mux|l1_w0_n0_mux_dataout~2_combout ;
wire \wrptr_g1p|counter4a4~q ;
wire \ws_dgrp|dffpipe8|dffe10a[4]~q ;
wire \wrptr_g1p|counter4a2~q ;
wire \ws_dgrp|dffpipe8|dffe10a[2]~q ;
wire \wrptr_g1p|counter4a3~q ;
wire \ws_dgrp|dffpipe8|dffe10a[3]~q ;
wire \wrptr_g1p|counter4a0~q ;
wire \ws_dgrp|dffpipe8|dffe10a[0]~q ;
wire \wrptr_g1p|counter4a1~q ;
wire \ws_dgrp|dffpipe8|dffe10a[1]~q ;
wire \wrfull_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~4_combout ;
wire \wrptr_g1p|counter4a6~q ;
wire \ws_dgrp|dffpipe8|dffe10a[6]~q ;
wire \wrfull_eq_comp1_msb|data_wire[0]~0_combout ;
wire \wrfull_eq_comp_msb|data_wire[0]~0_combout ;
wire \wrptr_g1p|counter4a7~q ;
wire \ws_dgrp|dffpipe8|dffe10a[7]~q ;
wire \wrptr_g1p|counter4a8~q ;
wire \ws_dgrp|dffpipe8|dffe10a[8]~q ;
wire \wrptr_g1p|counter4a5~q ;
wire \ws_dgrp|dffpipe8|dffe10a[5]~q ;
wire \wrfull_eq_comp_msb_mux|l1_w0_n0_mux_dataout~2_combout ;
wire \delayed_wrptr_g[4]~q ;
wire \delayed_wrptr_g[2]~q ;
wire \delayed_wrptr_g[3]~q ;
wire \delayed_wrptr_g[0]~q ;
wire \delayed_wrptr_g[1]~q ;
wire \delayed_wrptr_g[6]~q ;
wire \delayed_wrptr_g[7]~q ;
wire \delayed_wrptr_g[8]~q ;
wire \delayed_wrptr_g[5]~q ;
wire \wrptr_g[0]~0_combout ;
wire \rdptr_g[0]~0_combout ;
wire \rdptr_g1p|counter1a0~_wirecell_combout ;
wire \rdemp_eq_comp_lsb_aeb~q ;
wire \rdemp_eq_comp_msb_aeb~q ;
wire \wrfull_eq_comp_lsb_mux_reg~q ;
wire \wrfull_eq_comp_msb_mux_reg~q ;


cntrl_fifo_mux_ij7_3 wrfull_eq_comp_msb_mux(
	.int_wrfull(int_wrfull1),
	.wrptr_g_5(\wrptr_g[5]~q ),
	.wrptr_g_8(\wrptr_g[8]~q ),
	.wrptr_g_7(\wrptr_g[7]~q ),
	.data_wire_0(\wrfull_eq_comp1_msb|data_wire[0]~0_combout ),
	.data_wire_01(\wrfull_eq_comp_msb|data_wire[0]~0_combout ),
	.counter4a7(\wrptr_g1p|counter4a7~q ),
	.dffe10a_7(\ws_dgrp|dffpipe8|dffe10a[7]~q ),
	.counter4a8(\wrptr_g1p|counter4a8~q ),
	.dffe10a_8(\ws_dgrp|dffpipe8|dffe10a[8]~q ),
	.counter4a5(\wrptr_g1p|counter4a5~q ),
	.dffe10a_5(\ws_dgrp|dffpipe8|dffe10a[5]~q ),
	.l1_w0_n0_mux_dataout(\wrfull_eq_comp_msb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.wrreq(wrreq));

cntrl_fifo_mux_ij7_2 wrfull_eq_comp_lsb_mux(
	.int_wrfull(int_wrfull1),
	.wrptr_g_0(\wrptr_g[0]~q ),
	.wrptr_g_1(\wrptr_g[1]~q ),
	.wrptr_g_2(\wrptr_g[2]~q ),
	.wrptr_g_3(\wrptr_g[3]~q ),
	.wrptr_g_4(\wrptr_g[4]~q ),
	.counter4a4(\wrptr_g1p|counter4a4~q ),
	.dffe10a_4(\ws_dgrp|dffpipe8|dffe10a[4]~q ),
	.counter4a2(\wrptr_g1p|counter4a2~q ),
	.dffe10a_2(\ws_dgrp|dffpipe8|dffe10a[2]~q ),
	.counter4a3(\wrptr_g1p|counter4a3~q ),
	.dffe10a_3(\ws_dgrp|dffpipe8|dffe10a[3]~q ),
	.counter4a0(\wrptr_g1p|counter4a0~q ),
	.dffe10a_0(\ws_dgrp|dffpipe8|dffe10a[0]~q ),
	.counter4a1(\wrptr_g1p|counter4a1~q ),
	.dffe10a_1(\ws_dgrp|dffpipe8|dffe10a[1]~q ),
	.l1_w0_n0_mux_dataout(\wrfull_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~4_combout ),
	.wrreq(wrreq));

cntrl_fifo_mux_ij7_1 rdemp_eq_comp_msb_mux(
	.int_rdempty(int_rdempty1),
	.counter1a5(\rdptr_g1p|counter1a5~q ),
	.counter1a7(\rdptr_g1p|counter1a7~q ),
	.counter1a8(\rdptr_g1p|counter1a8~q ),
	.data_wire_0(\rdempty_eq_comp1_msb|data_wire[0]~0_combout ),
	.data_wire_01(\rdempty_eq_comp_msb|data_wire[0]~0_combout ),
	.dffe10a_7(\rs_dgwp|dffpipe8|dffe10a[7]~q ),
	.dffe10a_8(\rs_dgwp|dffpipe8|dffe10a[8]~q ),
	.dffe10a_5(\rs_dgwp|dffpipe8|dffe10a[5]~q ),
	.rdptr_g_7(\rdptr_g[7]~q ),
	.rdptr_g_8(\rdptr_g[8]~q ),
	.rdptr_g_5(\rdptr_g[5]~q ),
	.l1_w0_n0_mux_dataout(\rdemp_eq_comp_msb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.rdreq(rdreq));

cntrl_fifo_mux_ij7 rdemp_eq_comp_lsb_mux(
	.int_rdempty(int_rdempty1),
	.counter1a0(\rdptr_g1p|counter1a0~q ),
	.counter1a1(\rdptr_g1p|counter1a1~q ),
	.counter1a2(\rdptr_g1p|counter1a2~q ),
	.counter1a3(\rdptr_g1p|counter1a3~q ),
	.counter1a4(\rdptr_g1p|counter1a4~q ),
	.dffe10a_4(\rs_dgwp|dffpipe8|dffe10a[4]~q ),
	.dffe10a_2(\rs_dgwp|dffpipe8|dffe10a[2]~q ),
	.dffe10a_3(\rs_dgwp|dffpipe8|dffe10a[3]~q ),
	.dffe10a_0(\rs_dgwp|dffpipe8|dffe10a[0]~q ),
	.dffe10a_1(\rs_dgwp|dffpipe8|dffe10a[1]~q ),
	.rdptr_g_4(\rdptr_g[4]~q ),
	.rdptr_g_2(\rdptr_g[2]~q ),
	.rdptr_g_3(\rdptr_g[3]~q ),
	.rdptr_g_0(\rdptr_g[0]~q ),
	.rdptr_g_1(\rdptr_g[1]~q ),
	.l1_w0_n0_mux_dataout(\rdemp_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~4_combout ),
	.rdreq(rdreq));

cntrl_fifo_cmpr_9n5_3 wrfull_eq_comp_msb(
	.wrptr_g_6(\wrptr_g[6]~q ),
	.dffe10a_6(\ws_dgrp|dffpipe8|dffe10a[6]~q ),
	.data_wire_0(\wrfull_eq_comp_msb|data_wire[0]~0_combout ));

cntrl_fifo_cmpr_9n5_2 wrfull_eq_comp1_msb(
	.counter4a6(\wrptr_g1p|counter4a6~q ),
	.dffe10a_6(\ws_dgrp|dffpipe8|dffe10a[6]~q ),
	.data_wire_0(\wrfull_eq_comp1_msb|data_wire[0]~0_combout ));

cntrl_fifo_cmpr_9n5_1 rdempty_eq_comp_msb(
	.dffe10a_6(\rs_dgwp|dffpipe8|dffe10a[6]~q ),
	.rdptr_g_6(\rdptr_g[6]~q ),
	.data_wire_0(\rdempty_eq_comp_msb|data_wire[0]~0_combout ));

cntrl_fifo_cmpr_9n5 rdempty_eq_comp1_msb(
	.counter1a6(\rdptr_g1p|counter1a6~q ),
	.dffe10a_6(\rs_dgwp|dffpipe8|dffe10a[6]~q ),
	.data_wire_0(\rdempty_eq_comp1_msb|data_wire[0]~0_combout ));

cntrl_fifo_alt_synch_pipe_h9l_1 ws_dgrp(
	.rdptr_g_4(\rdptr_g[4]~q ),
	.rdptr_g_2(\rdptr_g[2]~q ),
	.rdptr_g_3(\rdptr_g[3]~q ),
	.rdptr_g_0(\rdptr_g[0]~q ),
	.rdptr_g_1(\rdptr_g[1]~q ),
	.rdptr_g_6(\rdptr_g[6]~q ),
	.rdptr_g_7(\rdptr_g[7]~q ),
	.rdptr_g_8(\rdptr_g[8]~q ),
	.rdptr_g_5(\rdptr_g[5]~q ),
	.dffe10a_4(\ws_dgrp|dffpipe8|dffe10a[4]~q ),
	.dffe10a_2(\ws_dgrp|dffpipe8|dffe10a[2]~q ),
	.dffe10a_3(\ws_dgrp|dffpipe8|dffe10a[3]~q ),
	.dffe10a_0(\ws_dgrp|dffpipe8|dffe10a[0]~q ),
	.dffe10a_1(\ws_dgrp|dffpipe8|dffe10a[1]~q ),
	.dffe10a_6(\ws_dgrp|dffpipe8|dffe10a[6]~q ),
	.dffe10a_7(\ws_dgrp|dffpipe8|dffe10a[7]~q ),
	.dffe10a_8(\ws_dgrp|dffpipe8|dffe10a[8]~q ),
	.dffe10a_5(\ws_dgrp|dffpipe8|dffe10a[5]~q ),
	.clock(wrclk));

cntrl_fifo_alt_synch_pipe_h9l rs_dgwp(
	.dffe10a_4(\rs_dgwp|dffpipe8|dffe10a[4]~q ),
	.dffe10a_2(\rs_dgwp|dffpipe8|dffe10a[2]~q ),
	.dffe10a_3(\rs_dgwp|dffpipe8|dffe10a[3]~q ),
	.dffe10a_0(\rs_dgwp|dffpipe8|dffe10a[0]~q ),
	.dffe10a_1(\rs_dgwp|dffpipe8|dffe10a[1]~q ),
	.dffe10a_6(\rs_dgwp|dffpipe8|dffe10a[6]~q ),
	.dffe10a_7(\rs_dgwp|dffpipe8|dffe10a[7]~q ),
	.dffe10a_8(\rs_dgwp|dffpipe8|dffe10a[8]~q ),
	.dffe10a_5(\rs_dgwp|dffpipe8|dffe10a[5]~q ),
	.delayed_wrptr_g_4(\delayed_wrptr_g[4]~q ),
	.delayed_wrptr_g_2(\delayed_wrptr_g[2]~q ),
	.delayed_wrptr_g_3(\delayed_wrptr_g[3]~q ),
	.delayed_wrptr_g_0(\delayed_wrptr_g[0]~q ),
	.delayed_wrptr_g_1(\delayed_wrptr_g[1]~q ),
	.delayed_wrptr_g_6(\delayed_wrptr_g[6]~q ),
	.delayed_wrptr_g_7(\delayed_wrptr_g[7]~q ),
	.delayed_wrptr_g_8(\delayed_wrptr_g[8]~q ),
	.delayed_wrptr_g_5(\delayed_wrptr_g[5]~q ),
	.clock(rdclk));

cntrl_fifo_altsyncram_j7a1 fifo_ram(
	.q_b({q[0]}),
	.wren_a(\valid_wrreq~0_combout ),
	.addressstall_b(\valid_rdreq~0_combout ),
	.clocken1(\valid_rdreq~0_combout ),
	.address_a({\ram_address_a[7]~combout ,\wrptr_g[6]~q ,\wrptr_g[5]~q ,\wrptr_g[4]~q ,\wrptr_g[3]~q ,\wrptr_g[2]~q ,\wrptr_g[1]~q ,\wrptr_g[0]~q }),
	.address_b({\rdptr_g1p|_~0_combout ,\rdptr_g1p|counter1a6~q ,\rdptr_g1p|counter1a5~q ,\rdptr_g1p|counter1a4~q ,\rdptr_g1p|counter1a3~q ,\rdptr_g1p|counter1a2~q ,\rdptr_g1p|counter1a1~q ,\rdptr_g1p|counter1a0~_wirecell_combout }),
	.clock0(wrclk),
	.clock1(rdclk),
	.data_a({data[0]}));

cntrl_fifo_a_graycounter_mmb wrptr_g1p(
	.wrfull_eq_comp_lsb_mux_reg(\wrfull_eq_comp_lsb_mux_reg~q ),
	.wrfull_eq_comp_msb_mux_reg(\wrfull_eq_comp_msb_mux_reg~q ),
	.int_wrfull(int_wrfull1),
	.valid_wrreq(\valid_wrreq~0_combout ),
	.counter4a41(\wrptr_g1p|counter4a4~q ),
	.counter4a21(\wrptr_g1p|counter4a2~q ),
	.counter4a31(\wrptr_g1p|counter4a3~q ),
	.counter4a01(\wrptr_g1p|counter4a0~q ),
	.counter4a11(\wrptr_g1p|counter4a1~q ),
	.counter4a61(\wrptr_g1p|counter4a6~q ),
	.counter4a71(\wrptr_g1p|counter4a7~q ),
	.counter4a81(\wrptr_g1p|counter4a8~q ),
	.counter4a51(\wrptr_g1p|counter4a5~q ),
	.wrreq(wrreq),
	.clock(wrclk));

cntrl_fifo_a_graycounter_q86 rdptr_g1p(
	.rdemp_eq_comp_lsb_aeb(\rdemp_eq_comp_lsb_aeb~q ),
	.rdemp_eq_comp_msb_aeb(\rdemp_eq_comp_msb_aeb~q ),
	.int_rdempty(int_rdempty1),
	.valid_rdreq(\valid_rdreq~0_combout ),
	.counter1a01(\rdptr_g1p|counter1a0~q ),
	.counter1a11(\rdptr_g1p|counter1a1~q ),
	.counter1a21(\rdptr_g1p|counter1a2~q ),
	.counter1a31(\rdptr_g1p|counter1a3~q ),
	.counter1a41(\rdptr_g1p|counter1a4~q ),
	.counter1a51(\rdptr_g1p|counter1a5~q ),
	.counter1a61(\rdptr_g1p|counter1a6~q ),
	.counter1a71(\rdptr_g1p|counter1a7~q ),
	.counter1a81(\rdptr_g1p|counter1a8~q ),
	._(\rdptr_g1p|_~0_combout ),
	.counter1a02(\rdptr_g1p|counter1a0~_wirecell_combout ),
	.rdreq(rdreq),
	.clock(rdclk));

twentynm_lcell_comb \valid_wrreq~0 (
	.dataa(!\wrfull_eq_comp_lsb_mux_reg~q ),
	.datab(!\wrfull_eq_comp_msb_mux_reg~q ),
	.datac(!wrreq),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\valid_wrreq~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \valid_wrreq~0 .extended_lut = "off";
defparam \valid_wrreq~0 .lut_mask = 64'h0E0E0E0E0E0E0E0E;
defparam \valid_wrreq~0 .shared_arith = "off";

twentynm_lcell_comb \valid_rdreq~0 (
	.dataa(!\rdemp_eq_comp_lsb_aeb~q ),
	.datab(!\rdemp_eq_comp_msb_aeb~q ),
	.datac(!rdreq),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\valid_rdreq~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \valid_rdreq~0 .extended_lut = "off";
defparam \valid_rdreq~0 .lut_mask = 64'h0707070707070707;
defparam \valid_rdreq~0 .shared_arith = "off";

dffeas \wrptr_g[0] (
	.clk(wrclk),
	.d(\wrptr_g[0]~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[0]~q ),
	.prn(vcc));
defparam \wrptr_g[0] .is_wysiwyg = "true";
defparam \wrptr_g[0] .power_up = "low";

dffeas \wrptr_g[1] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter4a1~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[1]~q ),
	.prn(vcc));
defparam \wrptr_g[1] .is_wysiwyg = "true";
defparam \wrptr_g[1] .power_up = "low";

dffeas \wrptr_g[2] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter4a2~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[2]~q ),
	.prn(vcc));
defparam \wrptr_g[2] .is_wysiwyg = "true";
defparam \wrptr_g[2] .power_up = "low";

dffeas \wrptr_g[3] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter4a3~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[3]~q ),
	.prn(vcc));
defparam \wrptr_g[3] .is_wysiwyg = "true";
defparam \wrptr_g[3] .power_up = "low";

dffeas \wrptr_g[4] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter4a4~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[4]~q ),
	.prn(vcc));
defparam \wrptr_g[4] .is_wysiwyg = "true";
defparam \wrptr_g[4] .power_up = "low";

dffeas \wrptr_g[5] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter4a5~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[5]~q ),
	.prn(vcc));
defparam \wrptr_g[5] .is_wysiwyg = "true";
defparam \wrptr_g[5] .power_up = "low";

dffeas \wrptr_g[6] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter4a6~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[6]~q ),
	.prn(vcc));
defparam \wrptr_g[6] .is_wysiwyg = "true";
defparam \wrptr_g[6] .power_up = "low";

dffeas \wrptr_g[8] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter4a8~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[8]~q ),
	.prn(vcc));
defparam \wrptr_g[8] .is_wysiwyg = "true";
defparam \wrptr_g[8] .power_up = "low";

dffeas \wrptr_g[7] (
	.clk(wrclk),
	.d(\wrptr_g1p|counter4a7~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_wrreq~0_combout ),
	.q(\wrptr_g[7]~q ),
	.prn(vcc));
defparam \wrptr_g[7] .is_wysiwyg = "true";
defparam \wrptr_g[7] .power_up = "low";

twentynm_lcell_comb \ram_address_a[7] (
	.dataa(!\wrptr_g[8]~q ),
	.datab(!\wrptr_g[7]~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\ram_address_a[7]~combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \ram_address_a[7] .extended_lut = "off";
defparam \ram_address_a[7] .lut_mask = 64'h6666666666666666;
defparam \ram_address_a[7] .shared_arith = "off";

dffeas \rdptr_g[4] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a4~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[4]~q ),
	.prn(vcc));
defparam \rdptr_g[4] .is_wysiwyg = "true";
defparam \rdptr_g[4] .power_up = "low";

dffeas \rdptr_g[2] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a2~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[2]~q ),
	.prn(vcc));
defparam \rdptr_g[2] .is_wysiwyg = "true";
defparam \rdptr_g[2] .power_up = "low";

dffeas \rdptr_g[3] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a3~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[3]~q ),
	.prn(vcc));
defparam \rdptr_g[3] .is_wysiwyg = "true";
defparam \rdptr_g[3] .power_up = "low";

dffeas \rdptr_g[0] (
	.clk(rdclk),
	.d(\rdptr_g[0]~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[0]~q ),
	.prn(vcc));
defparam \rdptr_g[0] .is_wysiwyg = "true";
defparam \rdptr_g[0] .power_up = "low";

dffeas \rdptr_g[1] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a1~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[1]~q ),
	.prn(vcc));
defparam \rdptr_g[1] .is_wysiwyg = "true";
defparam \rdptr_g[1] .power_up = "low";

dffeas \rdptr_g[6] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a6~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[6]~q ),
	.prn(vcc));
defparam \rdptr_g[6] .is_wysiwyg = "true";
defparam \rdptr_g[6] .power_up = "low";

dffeas \rdptr_g[7] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a7~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[7]~q ),
	.prn(vcc));
defparam \rdptr_g[7] .is_wysiwyg = "true";
defparam \rdptr_g[7] .power_up = "low";

dffeas \rdptr_g[8] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a8~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[8]~q ),
	.prn(vcc));
defparam \rdptr_g[8] .is_wysiwyg = "true";
defparam \rdptr_g[8] .power_up = "low";

dffeas \rdptr_g[5] (
	.clk(rdclk),
	.d(\rdptr_g1p|counter1a5~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\valid_rdreq~0_combout ),
	.q(\rdptr_g[5]~q ),
	.prn(vcc));
defparam \rdptr_g[5] .is_wysiwyg = "true";
defparam \rdptr_g[5] .power_up = "low";

dffeas \delayed_wrptr_g[4] (
	.clk(wrclk),
	.d(\wrptr_g[4]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[4]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[4] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[4] .power_up = "low";

dffeas \delayed_wrptr_g[2] (
	.clk(wrclk),
	.d(\wrptr_g[2]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[2]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[2] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[2] .power_up = "low";

dffeas \delayed_wrptr_g[3] (
	.clk(wrclk),
	.d(\wrptr_g[3]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[3]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[3] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[3] .power_up = "low";

dffeas \delayed_wrptr_g[0] (
	.clk(wrclk),
	.d(\wrptr_g[0]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[0]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[0] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[0] .power_up = "low";

dffeas \delayed_wrptr_g[1] (
	.clk(wrclk),
	.d(\wrptr_g[1]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[1]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[1] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[1] .power_up = "low";

dffeas \delayed_wrptr_g[6] (
	.clk(wrclk),
	.d(\wrptr_g[6]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[6]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[6] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[6] .power_up = "low";

dffeas \delayed_wrptr_g[7] (
	.clk(wrclk),
	.d(\wrptr_g[7]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[7]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[7] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[7] .power_up = "low";

dffeas \delayed_wrptr_g[8] (
	.clk(wrclk),
	.d(\wrptr_g[8]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[8]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[8] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[8] .power_up = "low";

dffeas \delayed_wrptr_g[5] (
	.clk(wrclk),
	.d(\wrptr_g[5]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\delayed_wrptr_g[5]~q ),
	.prn(vcc));
defparam \delayed_wrptr_g[5] .is_wysiwyg = "true";
defparam \delayed_wrptr_g[5] .power_up = "low";

twentynm_lcell_comb \wrptr_g[0]~0 (
	.dataa(!\wrptr_g1p|counter4a0~q ),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\wrptr_g[0]~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \wrptr_g[0]~0 .extended_lut = "off";
defparam \wrptr_g[0]~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \wrptr_g[0]~0 .shared_arith = "off";

twentynm_lcell_comb \rdptr_g[0]~0 (
	.dataa(!\rdptr_g1p|counter1a0~q ),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\rdptr_g[0]~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \rdptr_g[0]~0 .extended_lut = "off";
defparam \rdptr_g[0]~0 .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \rdptr_g[0]~0 .shared_arith = "off";

twentynm_lcell_comb int_rdempty(
	.dataa(!\rdemp_eq_comp_lsb_aeb~q ),
	.datab(!\rdemp_eq_comp_msb_aeb~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(int_rdempty1),
	.sumout(),
	.cout(),
	.shareout());
defparam int_rdempty.extended_lut = "off";
defparam int_rdempty.lut_mask = 64'h8888888888888888;
defparam int_rdempty.shared_arith = "off";

twentynm_lcell_comb int_wrfull(
	.dataa(!\wrfull_eq_comp_lsb_mux_reg~q ),
	.datab(!\wrfull_eq_comp_msb_mux_reg~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(int_wrfull1),
	.sumout(),
	.cout(),
	.shareout());
defparam int_wrfull.extended_lut = "off";
defparam int_wrfull.lut_mask = 64'h1111111111111111;
defparam int_wrfull.shared_arith = "off";

dffeas rdemp_eq_comp_lsb_aeb(
	.clk(rdclk),
	.d(\rdemp_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~4_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\rdemp_eq_comp_lsb_aeb~q ),
	.prn(vcc));
defparam rdemp_eq_comp_lsb_aeb.is_wysiwyg = "true";
defparam rdemp_eq_comp_lsb_aeb.power_up = "low";

dffeas rdemp_eq_comp_msb_aeb(
	.clk(rdclk),
	.d(\rdemp_eq_comp_msb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\rdemp_eq_comp_msb_aeb~q ),
	.prn(vcc));
defparam rdemp_eq_comp_msb_aeb.is_wysiwyg = "true";
defparam rdemp_eq_comp_msb_aeb.power_up = "low";

dffeas wrfull_eq_comp_lsb_mux_reg(
	.clk(wrclk),
	.d(\wrfull_eq_comp_lsb_mux|l1_w0_n0_mux_dataout~4_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\wrfull_eq_comp_lsb_mux_reg~q ),
	.prn(vcc));
defparam wrfull_eq_comp_lsb_mux_reg.is_wysiwyg = "true";
defparam wrfull_eq_comp_lsb_mux_reg.power_up = "low";

dffeas wrfull_eq_comp_msb_mux_reg(
	.clk(wrclk),
	.d(\wrfull_eq_comp_msb_mux|l1_w0_n0_mux_dataout~2_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\wrfull_eq_comp_msb_mux_reg~q ),
	.prn(vcc));
defparam wrfull_eq_comp_msb_mux_reg.is_wysiwyg = "true";
defparam wrfull_eq_comp_msb_mux_reg.power_up = "low";

endmodule

module cntrl_fifo_a_graycounter_mmb (
	wrfull_eq_comp_lsb_mux_reg,
	wrfull_eq_comp_msb_mux_reg,
	int_wrfull,
	valid_wrreq,
	counter4a41,
	counter4a21,
	counter4a31,
	counter4a01,
	counter4a11,
	counter4a61,
	counter4a71,
	counter4a81,
	counter4a51,
	wrreq,
	clock)/* synthesis synthesis_greybox=0 */;
input 	wrfull_eq_comp_lsb_mux_reg;
input 	wrfull_eq_comp_msb_mux_reg;
input 	int_wrfull;
input 	valid_wrreq;
output 	counter4a41;
output 	counter4a21;
output 	counter4a31;
output 	counter4a01;
output 	counter4a11;
output 	counter4a61;
output 	counter4a71;
output 	counter4a81;
output 	counter4a51;
input 	wrreq;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \_~4_combout ;
wire \sub_parity6a[1]~q ;
wire \_~5_combout ;
wire \sub_parity6a[0]~q ;
wire \_~3_combout ;
wire \parity5~q ;
wire \_~0_combout ;
wire \counter4a4~0_combout ;
wire \counter4a2~0_combout ;
wire \counter4a3~0_combout ;
wire \_~1_combout ;
wire \counter4a1~0_combout ;
wire \counter4a6~0_combout ;
wire \_~2_combout ;
wire \counter4a7~0_combout ;
wire \counter4a8~0_combout ;
wire \counter4a5~0_combout ;


dffeas counter4a4(
	.clk(clock),
	.d(\counter4a4~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter4a41),
	.prn(vcc));
defparam counter4a4.is_wysiwyg = "true";
defparam counter4a4.power_up = "low";

dffeas counter4a2(
	.clk(clock),
	.d(\counter4a2~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter4a21),
	.prn(vcc));
defparam counter4a2.is_wysiwyg = "true";
defparam counter4a2.power_up = "low";

dffeas counter4a3(
	.clk(clock),
	.d(\counter4a3~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter4a31),
	.prn(vcc));
defparam counter4a3.is_wysiwyg = "true";
defparam counter4a3.power_up = "low";

dffeas counter4a0(
	.clk(clock),
	.d(\_~1_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_wrreq),
	.q(counter4a01),
	.prn(vcc));
defparam counter4a0.is_wysiwyg = "true";
defparam counter4a0.power_up = "low";

dffeas counter4a1(
	.clk(clock),
	.d(\counter4a1~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter4a11),
	.prn(vcc));
defparam counter4a1.is_wysiwyg = "true";
defparam counter4a1.power_up = "low";

dffeas counter4a6(
	.clk(clock),
	.d(\counter4a6~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter4a61),
	.prn(vcc));
defparam counter4a6.is_wysiwyg = "true";
defparam counter4a6.power_up = "low";

dffeas counter4a7(
	.clk(clock),
	.d(\counter4a7~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter4a71),
	.prn(vcc));
defparam counter4a7.is_wysiwyg = "true";
defparam counter4a7.power_up = "low";

dffeas counter4a8(
	.clk(clock),
	.d(\counter4a8~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter4a81),
	.prn(vcc));
defparam counter4a8.is_wysiwyg = "true";
defparam counter4a8.power_up = "low";

dffeas counter4a5(
	.clk(clock),
	.d(\counter4a5~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter4a51),
	.prn(vcc));
defparam counter4a5.is_wysiwyg = "true";
defparam counter4a5.power_up = "low";

twentynm_lcell_comb \_~4 (
	.dataa(!counter4a71),
	.datab(!counter4a81),
	.datac(!counter4a61),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~4_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~4 .extended_lut = "off";
defparam \_~4 .lut_mask = 64'h6969696969696969;
defparam \_~4 .shared_arith = "off";

dffeas \sub_parity6a[1] (
	.clk(clock),
	.d(\_~4_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_wrreq),
	.q(\sub_parity6a[1]~q ),
	.prn(vcc));
defparam \sub_parity6a[1] .is_wysiwyg = "true";
defparam \sub_parity6a[1] .power_up = "low";

twentynm_lcell_comb \_~5 (
	.dataa(!counter4a41),
	.datab(!counter4a21),
	.datac(!counter4a31),
	.datad(!counter4a01),
	.datae(!counter4a11),
	.dataf(!counter4a51),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~5_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~5 .extended_lut = "off";
defparam \_~5 .lut_mask = 64'h9669699669969669;
defparam \_~5 .shared_arith = "off";

dffeas \sub_parity6a[0] (
	.clk(clock),
	.d(\_~5_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_wrreq),
	.q(\sub_parity6a[0]~q ),
	.prn(vcc));
defparam \sub_parity6a[0] .is_wysiwyg = "true";
defparam \sub_parity6a[0] .power_up = "low";

twentynm_lcell_comb \_~3 (
	.dataa(!\sub_parity6a[1]~q ),
	.datab(!\sub_parity6a[0]~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~3_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~3 .extended_lut = "off";
defparam \_~3 .lut_mask = 64'h9999999999999999;
defparam \_~3 .shared_arith = "off";

dffeas parity5(
	.clk(clock),
	.d(\_~3_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_wrreq),
	.q(\parity5~q ),
	.prn(vcc));
defparam parity5.is_wysiwyg = "true";
defparam parity5.power_up = "low";

twentynm_lcell_comb \_~0 (
	.dataa(!wrfull_eq_comp_lsb_mux_reg),
	.datab(!wrfull_eq_comp_msb_mux_reg),
	.datac(!wrreq),
	.datad(!counter4a01),
	.datae(!counter4a11),
	.dataf(!\parity5~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~0 .extended_lut = "off";
defparam \_~0 .lut_mask = 64'h000E000000000000;
defparam \_~0 .shared_arith = "off";

twentynm_lcell_comb \counter4a4~0 (
	.dataa(!counter4a41),
	.datab(!counter4a21),
	.datac(!counter4a31),
	.datad(!\_~0_combout ),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter4a4~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter4a4~0 .extended_lut = "off";
defparam \counter4a4~0 .lut_mask = 64'h5559555955595559;
defparam \counter4a4~0 .shared_arith = "off";

twentynm_lcell_comb \counter4a2~0 (
	.dataa(!int_wrfull),
	.datab(!wrreq),
	.datac(!counter4a21),
	.datad(!counter4a01),
	.datae(!counter4a11),
	.dataf(!\parity5~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter4a2~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter4a2~0 .extended_lut = "off";
defparam \counter4a2~0 .lut_mask = 64'h0F0F0F2D0F0F0F0F;
defparam \counter4a2~0 .shared_arith = "off";

twentynm_lcell_comb \counter4a3~0 (
	.dataa(!counter4a21),
	.datab(!counter4a31),
	.datac(!\_~0_combout ),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter4a3~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter4a3~0 .extended_lut = "off";
defparam \counter4a3~0 .lut_mask = 64'h3636363636363636;
defparam \counter4a3~0 .shared_arith = "off";

twentynm_lcell_comb \_~1 (
	.dataa(!counter4a01),
	.datab(!\parity5~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~1 .extended_lut = "off";
defparam \_~1 .lut_mask = 64'h6666666666666666;
defparam \_~1 .shared_arith = "off";

twentynm_lcell_comb \counter4a1~0 (
	.dataa(!wrfull_eq_comp_lsb_mux_reg),
	.datab(!wrfull_eq_comp_msb_mux_reg),
	.datac(!wrreq),
	.datad(!counter4a01),
	.datae(!counter4a11),
	.dataf(!\parity5~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter4a1~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter4a1~0 .extended_lut = "off";
defparam \counter4a1~0 .lut_mask = 64'h0E00F1FF0000FFFF;
defparam \counter4a1~0 .shared_arith = "off";

twentynm_lcell_comb \counter4a6~0 (
	.dataa(!counter4a41),
	.datab(!counter4a21),
	.datac(!counter4a31),
	.datad(!counter4a51),
	.datae(!counter4a61),
	.dataf(!\_~0_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter4a6~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter4a6~0 .extended_lut = "off";
defparam \counter4a6~0 .lut_mask = 64'h0000FFFF0080FF7F;
defparam \counter4a6~0 .shared_arith = "off";

twentynm_lcell_comb \_~2 (
	.dataa(!int_wrfull),
	.datab(!wrreq),
	.datac(!counter4a21),
	.datad(!counter4a01),
	.datae(!counter4a11),
	.dataf(!\parity5~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~2_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~2 .extended_lut = "off";
defparam \_~2 .lut_mask = 64'h0020000000000000;
defparam \_~2 .shared_arith = "off";

twentynm_lcell_comb \counter4a7~0 (
	.dataa(!counter4a41),
	.datab(!counter4a31),
	.datac(!counter4a71),
	.datad(!counter4a51),
	.datae(!counter4a61),
	.dataf(!\_~2_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter4a7~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter4a7~0 .extended_lut = "off";
defparam \counter4a7~0 .lut_mask = 64'h0F0F0F0F0F0F870F;
defparam \counter4a7~0 .shared_arith = "off";

twentynm_lcell_comb \counter4a8~0 (
	.dataa(!counter4a41),
	.datab(!counter4a31),
	.datac(!counter4a81),
	.datad(!counter4a51),
	.datae(!counter4a61),
	.dataf(!\_~2_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter4a8~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter4a8~0 .extended_lut = "off";
defparam \counter4a8~0 .lut_mask = 64'h0F0F0F0F870F0F0F;
defparam \counter4a8~0 .shared_arith = "off";

twentynm_lcell_comb \counter4a5~0 (
	.dataa(!counter4a41),
	.datab(!counter4a21),
	.datac(!counter4a31),
	.datad(!counter4a51),
	.datae(!\_~0_combout ),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter4a5~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter4a5~0 .extended_lut = "off";
defparam \counter4a5~0 .lut_mask = 64'h00FF40BF00FF40BF;
defparam \counter4a5~0 .shared_arith = "off";

endmodule

module cntrl_fifo_a_graycounter_q86 (
	rdemp_eq_comp_lsb_aeb,
	rdemp_eq_comp_msb_aeb,
	int_rdempty,
	valid_rdreq,
	counter1a01,
	counter1a11,
	counter1a21,
	counter1a31,
	counter1a41,
	counter1a51,
	counter1a61,
	counter1a71,
	counter1a81,
	_,
	counter1a02,
	rdreq,
	clock)/* synthesis synthesis_greybox=0 */;
input 	rdemp_eq_comp_lsb_aeb;
input 	rdemp_eq_comp_msb_aeb;
input 	int_rdempty;
input 	valid_rdreq;
output 	counter1a01;
output 	counter1a11;
output 	counter1a21;
output 	counter1a31;
output 	counter1a41;
output 	counter1a51;
output 	counter1a61;
output 	counter1a71;
output 	counter1a81;
output 	_;
output 	counter1a02;
input 	rdreq;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \_~5_combout ;
wire \sub_parity3a[1]~q ;
wire \_~6_combout ;
wire \sub_parity3a[0]~q ;
wire \_~4_combout ;
wire \parity2~q ;
wire \_~1_combout ;
wire \counter1a1~0_combout ;
wire \counter1a2~0_combout ;
wire \_~2_combout ;
wire \counter1a3~0_combout ;
wire \counter1a4~0_combout ;
wire \counter1a5~0_combout ;
wire \counter1a6~0_combout ;
wire \_~3_combout ;
wire \counter1a7~0_combout ;
wire \counter1a8~0_combout ;


dffeas counter1a0(
	.clk(clock),
	.d(\_~1_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_rdreq),
	.q(counter1a01),
	.prn(vcc));
defparam counter1a0.is_wysiwyg = "true";
defparam counter1a0.power_up = "low";

dffeas counter1a1(
	.clk(clock),
	.d(\counter1a1~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a11),
	.prn(vcc));
defparam counter1a1.is_wysiwyg = "true";
defparam counter1a1.power_up = "low";

dffeas counter1a2(
	.clk(clock),
	.d(\counter1a2~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a21),
	.prn(vcc));
defparam counter1a2.is_wysiwyg = "true";
defparam counter1a2.power_up = "low";

dffeas counter1a3(
	.clk(clock),
	.d(\counter1a3~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a31),
	.prn(vcc));
defparam counter1a3.is_wysiwyg = "true";
defparam counter1a3.power_up = "low";

dffeas counter1a4(
	.clk(clock),
	.d(\counter1a4~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a41),
	.prn(vcc));
defparam counter1a4.is_wysiwyg = "true";
defparam counter1a4.power_up = "low";

dffeas counter1a5(
	.clk(clock),
	.d(\counter1a5~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a51),
	.prn(vcc));
defparam counter1a5.is_wysiwyg = "true";
defparam counter1a5.power_up = "low";

dffeas counter1a6(
	.clk(clock),
	.d(\counter1a6~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a61),
	.prn(vcc));
defparam counter1a6.is_wysiwyg = "true";
defparam counter1a6.power_up = "low";

dffeas counter1a7(
	.clk(clock),
	.d(\counter1a7~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a71),
	.prn(vcc));
defparam counter1a7.is_wysiwyg = "true";
defparam counter1a7.power_up = "low";

dffeas counter1a8(
	.clk(clock),
	.d(\counter1a8~0_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(counter1a81),
	.prn(vcc));
defparam counter1a8.is_wysiwyg = "true";
defparam counter1a8.power_up = "low";

twentynm_lcell_comb \_~0 (
	.dataa(!counter1a71),
	.datab(!counter1a81),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(_),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~0 .extended_lut = "off";
defparam \_~0 .lut_mask = 64'h6666666666666666;
defparam \_~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a0~_wirecell (
	.dataa(!counter1a01),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(counter1a02),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a0~_wirecell .extended_lut = "off";
defparam \counter1a0~_wirecell .lut_mask = 64'hAAAAAAAAAAAAAAAA;
defparam \counter1a0~_wirecell .shared_arith = "off";

twentynm_lcell_comb \_~5 (
	.dataa(!counter1a61),
	.datab(!counter1a71),
	.datac(!counter1a81),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~5_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~5 .extended_lut = "off";
defparam \_~5 .lut_mask = 64'h6969696969696969;
defparam \_~5 .shared_arith = "off";

dffeas \sub_parity3a[1] (
	.clk(clock),
	.d(\_~5_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_rdreq),
	.q(\sub_parity3a[1]~q ),
	.prn(vcc));
defparam \sub_parity3a[1] .is_wysiwyg = "true";
defparam \sub_parity3a[1] .power_up = "low";

twentynm_lcell_comb \_~6 (
	.dataa(!counter1a01),
	.datab(!counter1a11),
	.datac(!counter1a21),
	.datad(!counter1a31),
	.datae(!counter1a41),
	.dataf(!counter1a51),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~6_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~6 .extended_lut = "off";
defparam \_~6 .lut_mask = 64'h9669699669969669;
defparam \_~6 .shared_arith = "off";

dffeas \sub_parity3a[0] (
	.clk(clock),
	.d(\_~6_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_rdreq),
	.q(\sub_parity3a[0]~q ),
	.prn(vcc));
defparam \sub_parity3a[0] .is_wysiwyg = "true";
defparam \sub_parity3a[0] .power_up = "low";

twentynm_lcell_comb \_~4 (
	.dataa(!\sub_parity3a[1]~q ),
	.datab(!\sub_parity3a[0]~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~4_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~4 .extended_lut = "off";
defparam \_~4 .lut_mask = 64'h9999999999999999;
defparam \_~4 .shared_arith = "off";

dffeas parity2(
	.clk(clock),
	.d(\_~4_combout ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(valid_rdreq),
	.q(\parity2~q ),
	.prn(vcc));
defparam parity2.is_wysiwyg = "true";
defparam parity2.power_up = "low";

twentynm_lcell_comb \_~1 (
	.dataa(!counter1a01),
	.datab(!\parity2~q ),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~1 .extended_lut = "off";
defparam \_~1 .lut_mask = 64'h6666666666666666;
defparam \_~1 .shared_arith = "off";

twentynm_lcell_comb \counter1a1~0 (
	.dataa(!rdemp_eq_comp_lsb_aeb),
	.datab(!rdemp_eq_comp_msb_aeb),
	.datac(!rdreq),
	.datad(!counter1a01),
	.datae(!counter1a11),
	.dataf(!\parity2~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a1~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a1~0 .extended_lut = "off";
defparam \counter1a1~0 .lut_mask = 64'h0700F8FF0000FFFF;
defparam \counter1a1~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a2~0 (
	.dataa(!int_rdempty),
	.datab(!rdreq),
	.datac(!counter1a01),
	.datad(!counter1a11),
	.datae(!counter1a21),
	.dataf(!\parity2~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a2~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a2~0 .extended_lut = "off";
defparam \counter1a2~0 .lut_mask = 64'h0002FFFD0000FFFF;
defparam \counter1a2~0 .shared_arith = "off";

twentynm_lcell_comb \_~2 (
	.dataa(!rdemp_eq_comp_lsb_aeb),
	.datab(!rdemp_eq_comp_msb_aeb),
	.datac(!rdreq),
	.datad(!counter1a01),
	.datae(!counter1a11),
	.dataf(!\parity2~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~2_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~2 .extended_lut = "off";
defparam \_~2 .lut_mask = 64'h0007000000000000;
defparam \_~2 .shared_arith = "off";

twentynm_lcell_comb \counter1a3~0 (
	.dataa(!counter1a21),
	.datab(!counter1a31),
	.datac(!\_~2_combout ),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a3~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a3~0 .extended_lut = "off";
defparam \counter1a3~0 .lut_mask = 64'h3636363636363636;
defparam \counter1a3~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a4~0 (
	.dataa(!counter1a21),
	.datab(!counter1a31),
	.datac(!counter1a41),
	.datad(!\_~2_combout ),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a4~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a4~0 .extended_lut = "off";
defparam \counter1a4~0 .lut_mask = 64'h0F2D0F2D0F2D0F2D;
defparam \counter1a4~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a5~0 (
	.dataa(!counter1a21),
	.datab(!counter1a31),
	.datac(!counter1a41),
	.datad(!counter1a51),
	.datae(!\_~2_combout ),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a5~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a5~0 .extended_lut = "off";
defparam \counter1a5~0 .lut_mask = 64'h00FF08F700FF08F7;
defparam \counter1a5~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a6~0 (
	.dataa(!counter1a21),
	.datab(!counter1a31),
	.datac(!counter1a41),
	.datad(!counter1a51),
	.datae(!counter1a61),
	.dataf(!\_~2_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a6~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a6~0 .extended_lut = "off";
defparam \counter1a6~0 .lut_mask = 64'h0000FFFF0080FF7F;
defparam \counter1a6~0 .shared_arith = "off";

twentynm_lcell_comb \_~3 (
	.dataa(!int_rdempty),
	.datab(!rdreq),
	.datac(!counter1a01),
	.datad(!counter1a11),
	.datae(!counter1a21),
	.dataf(!\parity2~q ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\_~3_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \_~3 .extended_lut = "off";
defparam \_~3 .lut_mask = 64'h0200000000000000;
defparam \_~3 .shared_arith = "off";

twentynm_lcell_comb \counter1a7~0 (
	.dataa(!counter1a31),
	.datab(!counter1a41),
	.datac(!counter1a51),
	.datad(!counter1a61),
	.datae(!counter1a71),
	.dataf(!\_~3_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a7~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a7~0 .extended_lut = "off";
defparam \counter1a7~0 .lut_mask = 64'h0000FFFF0080FF7F;
defparam \counter1a7~0 .shared_arith = "off";

twentynm_lcell_comb \counter1a8~0 (
	.dataa(!counter1a31),
	.datab(!counter1a41),
	.datac(!counter1a51),
	.datad(!counter1a61),
	.datae(!counter1a81),
	.dataf(!\_~3_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\counter1a8~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \counter1a8~0 .extended_lut = "off";
defparam \counter1a8~0 .lut_mask = 64'h0000FFFF80007FFF;
defparam \counter1a8~0 .shared_arith = "off";

endmodule

module cntrl_fifo_alt_synch_pipe_h9l (
	dffe10a_4,
	dffe10a_2,
	dffe10a_3,
	dffe10a_0,
	dffe10a_1,
	dffe10a_6,
	dffe10a_7,
	dffe10a_8,
	dffe10a_5,
	delayed_wrptr_g_4,
	delayed_wrptr_g_2,
	delayed_wrptr_g_3,
	delayed_wrptr_g_0,
	delayed_wrptr_g_1,
	delayed_wrptr_g_6,
	delayed_wrptr_g_7,
	delayed_wrptr_g_8,
	delayed_wrptr_g_5,
	clock)/* synthesis synthesis_greybox=0 */;
output 	dffe10a_4;
output 	dffe10a_2;
output 	dffe10a_3;
output 	dffe10a_0;
output 	dffe10a_1;
output 	dffe10a_6;
output 	dffe10a_7;
output 	dffe10a_8;
output 	dffe10a_5;
input 	delayed_wrptr_g_4;
input 	delayed_wrptr_g_2;
input 	delayed_wrptr_g_3;
input 	delayed_wrptr_g_0;
input 	delayed_wrptr_g_1;
input 	delayed_wrptr_g_6;
input 	delayed_wrptr_g_7;
input 	delayed_wrptr_g_8;
input 	delayed_wrptr_g_5;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



cntrl_fifo_dffpipe_2v8 dffpipe8(
	.dffe10a_4(dffe10a_4),
	.dffe10a_2(dffe10a_2),
	.dffe10a_3(dffe10a_3),
	.dffe10a_0(dffe10a_0),
	.dffe10a_1(dffe10a_1),
	.dffe10a_6(dffe10a_6),
	.dffe10a_7(dffe10a_7),
	.dffe10a_8(dffe10a_8),
	.dffe10a_5(dffe10a_5),
	.delayed_wrptr_g_4(delayed_wrptr_g_4),
	.delayed_wrptr_g_2(delayed_wrptr_g_2),
	.delayed_wrptr_g_3(delayed_wrptr_g_3),
	.delayed_wrptr_g_0(delayed_wrptr_g_0),
	.delayed_wrptr_g_1(delayed_wrptr_g_1),
	.delayed_wrptr_g_6(delayed_wrptr_g_6),
	.delayed_wrptr_g_7(delayed_wrptr_g_7),
	.delayed_wrptr_g_8(delayed_wrptr_g_8),
	.delayed_wrptr_g_5(delayed_wrptr_g_5),
	.clock(clock));

endmodule

module cntrl_fifo_dffpipe_2v8 (
	dffe10a_4,
	dffe10a_2,
	dffe10a_3,
	dffe10a_0,
	dffe10a_1,
	dffe10a_6,
	dffe10a_7,
	dffe10a_8,
	dffe10a_5,
	delayed_wrptr_g_4,
	delayed_wrptr_g_2,
	delayed_wrptr_g_3,
	delayed_wrptr_g_0,
	delayed_wrptr_g_1,
	delayed_wrptr_g_6,
	delayed_wrptr_g_7,
	delayed_wrptr_g_8,
	delayed_wrptr_g_5,
	clock)/* synthesis synthesis_greybox=0 */;
output 	dffe10a_4;
output 	dffe10a_2;
output 	dffe10a_3;
output 	dffe10a_0;
output 	dffe10a_1;
output 	dffe10a_6;
output 	dffe10a_7;
output 	dffe10a_8;
output 	dffe10a_5;
input 	delayed_wrptr_g_4;
input 	delayed_wrptr_g_2;
input 	delayed_wrptr_g_3;
input 	delayed_wrptr_g_0;
input 	delayed_wrptr_g_1;
input 	delayed_wrptr_g_6;
input 	delayed_wrptr_g_7;
input 	delayed_wrptr_g_8;
input 	delayed_wrptr_g_5;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \dffe9a[4]~q ;
wire \dffe9a[2]~q ;
wire \dffe9a[3]~q ;
wire \dffe9a[0]~q ;
wire \dffe9a[1]~q ;
wire \dffe9a[6]~q ;
wire \dffe9a[7]~q ;
wire \dffe9a[8]~q ;
wire \dffe9a[5]~q ;


dffeas \dffe10a[4] (
	.clk(clock),
	.d(\dffe9a[4]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_4),
	.prn(vcc));
defparam \dffe10a[4] .is_wysiwyg = "true";
defparam \dffe10a[4] .power_up = "low";
defparam \dffe10a[4] .x_on_violation = "off";

dffeas \dffe10a[2] (
	.clk(clock),
	.d(\dffe9a[2]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_2),
	.prn(vcc));
defparam \dffe10a[2] .is_wysiwyg = "true";
defparam \dffe10a[2] .power_up = "low";
defparam \dffe10a[2] .x_on_violation = "off";

dffeas \dffe10a[3] (
	.clk(clock),
	.d(\dffe9a[3]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_3),
	.prn(vcc));
defparam \dffe10a[3] .is_wysiwyg = "true";
defparam \dffe10a[3] .power_up = "low";
defparam \dffe10a[3] .x_on_violation = "off";

dffeas \dffe10a[0] (
	.clk(clock),
	.d(\dffe9a[0]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_0),
	.prn(vcc));
defparam \dffe10a[0] .is_wysiwyg = "true";
defparam \dffe10a[0] .power_up = "low";
defparam \dffe10a[0] .x_on_violation = "off";

dffeas \dffe10a[1] (
	.clk(clock),
	.d(\dffe9a[1]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_1),
	.prn(vcc));
defparam \dffe10a[1] .is_wysiwyg = "true";
defparam \dffe10a[1] .power_up = "low";
defparam \dffe10a[1] .x_on_violation = "off";

dffeas \dffe10a[6] (
	.clk(clock),
	.d(\dffe9a[6]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_6),
	.prn(vcc));
defparam \dffe10a[6] .is_wysiwyg = "true";
defparam \dffe10a[6] .power_up = "low";
defparam \dffe10a[6] .x_on_violation = "off";

dffeas \dffe10a[7] (
	.clk(clock),
	.d(\dffe9a[7]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_7),
	.prn(vcc));
defparam \dffe10a[7] .is_wysiwyg = "true";
defparam \dffe10a[7] .power_up = "low";
defparam \dffe10a[7] .x_on_violation = "off";

dffeas \dffe10a[8] (
	.clk(clock),
	.d(\dffe9a[8]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_8),
	.prn(vcc));
defparam \dffe10a[8] .is_wysiwyg = "true";
defparam \dffe10a[8] .power_up = "low";
defparam \dffe10a[8] .x_on_violation = "off";

dffeas \dffe10a[5] (
	.clk(clock),
	.d(\dffe9a[5]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_5),
	.prn(vcc));
defparam \dffe10a[5] .is_wysiwyg = "true";
defparam \dffe10a[5] .power_up = "low";
defparam \dffe10a[5] .x_on_violation = "off";

dffeas \dffe9a[4] (
	.clk(clock),
	.d(delayed_wrptr_g_4),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[4]~q ),
	.prn(vcc));
defparam \dffe9a[4] .is_wysiwyg = "true";
defparam \dffe9a[4] .power_up = "low";
defparam \dffe9a[4] .x_on_violation = "off";

dffeas \dffe9a[2] (
	.clk(clock),
	.d(delayed_wrptr_g_2),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[2]~q ),
	.prn(vcc));
defparam \dffe9a[2] .is_wysiwyg = "true";
defparam \dffe9a[2] .power_up = "low";
defparam \dffe9a[2] .x_on_violation = "off";

dffeas \dffe9a[3] (
	.clk(clock),
	.d(delayed_wrptr_g_3),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[3]~q ),
	.prn(vcc));
defparam \dffe9a[3] .is_wysiwyg = "true";
defparam \dffe9a[3] .power_up = "low";
defparam \dffe9a[3] .x_on_violation = "off";

dffeas \dffe9a[0] (
	.clk(clock),
	.d(delayed_wrptr_g_0),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[0]~q ),
	.prn(vcc));
defparam \dffe9a[0] .is_wysiwyg = "true";
defparam \dffe9a[0] .power_up = "low";
defparam \dffe9a[0] .x_on_violation = "off";

dffeas \dffe9a[1] (
	.clk(clock),
	.d(delayed_wrptr_g_1),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[1]~q ),
	.prn(vcc));
defparam \dffe9a[1] .is_wysiwyg = "true";
defparam \dffe9a[1] .power_up = "low";
defparam \dffe9a[1] .x_on_violation = "off";

dffeas \dffe9a[6] (
	.clk(clock),
	.d(delayed_wrptr_g_6),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[6]~q ),
	.prn(vcc));
defparam \dffe9a[6] .is_wysiwyg = "true";
defparam \dffe9a[6] .power_up = "low";
defparam \dffe9a[6] .x_on_violation = "off";

dffeas \dffe9a[7] (
	.clk(clock),
	.d(delayed_wrptr_g_7),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[7]~q ),
	.prn(vcc));
defparam \dffe9a[7] .is_wysiwyg = "true";
defparam \dffe9a[7] .power_up = "low";
defparam \dffe9a[7] .x_on_violation = "off";

dffeas \dffe9a[8] (
	.clk(clock),
	.d(delayed_wrptr_g_8),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[8]~q ),
	.prn(vcc));
defparam \dffe9a[8] .is_wysiwyg = "true";
defparam \dffe9a[8] .power_up = "low";
defparam \dffe9a[8] .x_on_violation = "off";

dffeas \dffe9a[5] (
	.clk(clock),
	.d(delayed_wrptr_g_5),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[5]~q ),
	.prn(vcc));
defparam \dffe9a[5] .is_wysiwyg = "true";
defparam \dffe9a[5] .power_up = "low";
defparam \dffe9a[5] .x_on_violation = "off";

endmodule

module cntrl_fifo_alt_synch_pipe_h9l_1 (
	rdptr_g_4,
	rdptr_g_2,
	rdptr_g_3,
	rdptr_g_0,
	rdptr_g_1,
	rdptr_g_6,
	rdptr_g_7,
	rdptr_g_8,
	rdptr_g_5,
	dffe10a_4,
	dffe10a_2,
	dffe10a_3,
	dffe10a_0,
	dffe10a_1,
	dffe10a_6,
	dffe10a_7,
	dffe10a_8,
	dffe10a_5,
	clock)/* synthesis synthesis_greybox=0 */;
input 	rdptr_g_4;
input 	rdptr_g_2;
input 	rdptr_g_3;
input 	rdptr_g_0;
input 	rdptr_g_1;
input 	rdptr_g_6;
input 	rdptr_g_7;
input 	rdptr_g_8;
input 	rdptr_g_5;
output 	dffe10a_4;
output 	dffe10a_2;
output 	dffe10a_3;
output 	dffe10a_0;
output 	dffe10a_1;
output 	dffe10a_6;
output 	dffe10a_7;
output 	dffe10a_8;
output 	dffe10a_5;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



cntrl_fifo_dffpipe_2v8_1 dffpipe8(
	.rdptr_g_4(rdptr_g_4),
	.rdptr_g_2(rdptr_g_2),
	.rdptr_g_3(rdptr_g_3),
	.rdptr_g_0(rdptr_g_0),
	.rdptr_g_1(rdptr_g_1),
	.rdptr_g_6(rdptr_g_6),
	.rdptr_g_7(rdptr_g_7),
	.rdptr_g_8(rdptr_g_8),
	.rdptr_g_5(rdptr_g_5),
	.dffe10a_4(dffe10a_4),
	.dffe10a_2(dffe10a_2),
	.dffe10a_3(dffe10a_3),
	.dffe10a_0(dffe10a_0),
	.dffe10a_1(dffe10a_1),
	.dffe10a_6(dffe10a_6),
	.dffe10a_7(dffe10a_7),
	.dffe10a_8(dffe10a_8),
	.dffe10a_5(dffe10a_5),
	.clock(clock));

endmodule

module cntrl_fifo_dffpipe_2v8_1 (
	rdptr_g_4,
	rdptr_g_2,
	rdptr_g_3,
	rdptr_g_0,
	rdptr_g_1,
	rdptr_g_6,
	rdptr_g_7,
	rdptr_g_8,
	rdptr_g_5,
	dffe10a_4,
	dffe10a_2,
	dffe10a_3,
	dffe10a_0,
	dffe10a_1,
	dffe10a_6,
	dffe10a_7,
	dffe10a_8,
	dffe10a_5,
	clock)/* synthesis synthesis_greybox=0 */;
input 	rdptr_g_4;
input 	rdptr_g_2;
input 	rdptr_g_3;
input 	rdptr_g_0;
input 	rdptr_g_1;
input 	rdptr_g_6;
input 	rdptr_g_7;
input 	rdptr_g_8;
input 	rdptr_g_5;
output 	dffe10a_4;
output 	dffe10a_2;
output 	dffe10a_3;
output 	dffe10a_0;
output 	dffe10a_1;
output 	dffe10a_6;
output 	dffe10a_7;
output 	dffe10a_8;
output 	dffe10a_5;
input 	clock;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \dffe9a[4]~q ;
wire \dffe9a[2]~q ;
wire \dffe9a[3]~q ;
wire \dffe9a[0]~q ;
wire \dffe9a[1]~q ;
wire \dffe9a[6]~q ;
wire \dffe9a[7]~q ;
wire \dffe9a[8]~q ;
wire \dffe9a[5]~q ;


dffeas \dffe10a[4] (
	.clk(clock),
	.d(\dffe9a[4]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_4),
	.prn(vcc));
defparam \dffe10a[4] .is_wysiwyg = "true";
defparam \dffe10a[4] .power_up = "low";
defparam \dffe10a[4] .x_on_violation = "off";

dffeas \dffe10a[2] (
	.clk(clock),
	.d(\dffe9a[2]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_2),
	.prn(vcc));
defparam \dffe10a[2] .is_wysiwyg = "true";
defparam \dffe10a[2] .power_up = "low";
defparam \dffe10a[2] .x_on_violation = "off";

dffeas \dffe10a[3] (
	.clk(clock),
	.d(\dffe9a[3]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_3),
	.prn(vcc));
defparam \dffe10a[3] .is_wysiwyg = "true";
defparam \dffe10a[3] .power_up = "low";
defparam \dffe10a[3] .x_on_violation = "off";

dffeas \dffe10a[0] (
	.clk(clock),
	.d(\dffe9a[0]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_0),
	.prn(vcc));
defparam \dffe10a[0] .is_wysiwyg = "true";
defparam \dffe10a[0] .power_up = "low";
defparam \dffe10a[0] .x_on_violation = "off";

dffeas \dffe10a[1] (
	.clk(clock),
	.d(\dffe9a[1]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_1),
	.prn(vcc));
defparam \dffe10a[1] .is_wysiwyg = "true";
defparam \dffe10a[1] .power_up = "low";
defparam \dffe10a[1] .x_on_violation = "off";

dffeas \dffe10a[6] (
	.clk(clock),
	.d(\dffe9a[6]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_6),
	.prn(vcc));
defparam \dffe10a[6] .is_wysiwyg = "true";
defparam \dffe10a[6] .power_up = "low";
defparam \dffe10a[6] .x_on_violation = "off";

dffeas \dffe10a[7] (
	.clk(clock),
	.d(\dffe9a[7]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_7),
	.prn(vcc));
defparam \dffe10a[7] .is_wysiwyg = "true";
defparam \dffe10a[7] .power_up = "low";
defparam \dffe10a[7] .x_on_violation = "off";

dffeas \dffe10a[8] (
	.clk(clock),
	.d(\dffe9a[8]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_8),
	.prn(vcc));
defparam \dffe10a[8] .is_wysiwyg = "true";
defparam \dffe10a[8] .power_up = "low";
defparam \dffe10a[8] .x_on_violation = "off";

dffeas \dffe10a[5] (
	.clk(clock),
	.d(\dffe9a[5]~q ),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(dffe10a_5),
	.prn(vcc));
defparam \dffe10a[5] .is_wysiwyg = "true";
defparam \dffe10a[5] .power_up = "low";
defparam \dffe10a[5] .x_on_violation = "off";

dffeas \dffe9a[4] (
	.clk(clock),
	.d(rdptr_g_4),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[4]~q ),
	.prn(vcc));
defparam \dffe9a[4] .is_wysiwyg = "true";
defparam \dffe9a[4] .power_up = "low";
defparam \dffe9a[4] .x_on_violation = "off";

dffeas \dffe9a[2] (
	.clk(clock),
	.d(rdptr_g_2),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[2]~q ),
	.prn(vcc));
defparam \dffe9a[2] .is_wysiwyg = "true";
defparam \dffe9a[2] .power_up = "low";
defparam \dffe9a[2] .x_on_violation = "off";

dffeas \dffe9a[3] (
	.clk(clock),
	.d(rdptr_g_3),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[3]~q ),
	.prn(vcc));
defparam \dffe9a[3] .is_wysiwyg = "true";
defparam \dffe9a[3] .power_up = "low";
defparam \dffe9a[3] .x_on_violation = "off";

dffeas \dffe9a[0] (
	.clk(clock),
	.d(rdptr_g_0),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[0]~q ),
	.prn(vcc));
defparam \dffe9a[0] .is_wysiwyg = "true";
defparam \dffe9a[0] .power_up = "low";
defparam \dffe9a[0] .x_on_violation = "off";

dffeas \dffe9a[1] (
	.clk(clock),
	.d(rdptr_g_1),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[1]~q ),
	.prn(vcc));
defparam \dffe9a[1] .is_wysiwyg = "true";
defparam \dffe9a[1] .power_up = "low";
defparam \dffe9a[1] .x_on_violation = "off";

dffeas \dffe9a[6] (
	.clk(clock),
	.d(rdptr_g_6),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[6]~q ),
	.prn(vcc));
defparam \dffe9a[6] .is_wysiwyg = "true";
defparam \dffe9a[6] .power_up = "low";
defparam \dffe9a[6] .x_on_violation = "off";

dffeas \dffe9a[7] (
	.clk(clock),
	.d(rdptr_g_7),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[7]~q ),
	.prn(vcc));
defparam \dffe9a[7] .is_wysiwyg = "true";
defparam \dffe9a[7] .power_up = "low";
defparam \dffe9a[7] .x_on_violation = "off";

dffeas \dffe9a[8] (
	.clk(clock),
	.d(rdptr_g_8),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[8]~q ),
	.prn(vcc));
defparam \dffe9a[8] .is_wysiwyg = "true";
defparam \dffe9a[8] .power_up = "low";
defparam \dffe9a[8] .x_on_violation = "off";

dffeas \dffe9a[5] (
	.clk(clock),
	.d(rdptr_g_5),
	.asdata(vcc),
	.clrn(vcc),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.q(\dffe9a[5]~q ),
	.prn(vcc));
defparam \dffe9a[5] .is_wysiwyg = "true";
defparam \dffe9a[5] .power_up = "low";
defparam \dffe9a[5] .x_on_violation = "off";

endmodule

module cntrl_fifo_altsyncram_j7a1 (
	q_b,
	wren_a,
	addressstall_b,
	clocken1,
	address_a,
	address_b,
	clock0,
	clock1,
	data_a)/* synthesis synthesis_greybox=0 */;
output 	[0:0] q_b;
input 	wren_a;
input 	addressstall_b;
input 	clocken1;
input 	[7:0] address_a;
input 	[7:0] address_b;
input 	clock0;
input 	clock1;
input 	[0:0] data_a;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;


wire [143:0] ram_block7a0_PORTBDATAOUT_bus;

assign q_b[0] = ram_block7a0_PORTBDATAOUT_bus[0];

twentynm_ram_block ram_block7a0(
	.portawe(wren_a),
	.portare(vcc),
	.portaaddrstall(gnd),
	.portbwe(gnd),
	.portbre(vcc),
	.portbaddrstall(!addressstall_b),
	.clk0(clock0),
	.clk1(clock1),
	.ena0(wren_a),
	.ena1(addressstall_b),
	.ena2(vcc),
	.ena3(vcc),
	.clr0(gnd),
	.clr1(gnd),
	.nerror(vcc),
	.portadatain({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,
gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,data_a[0]}),
	.portaaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),
	.portabyteenamasks(1'b1),
	.portbdatain(1'b0),
	.portbaddr({gnd,gnd,gnd,gnd,gnd,gnd,gnd,gnd,address_b[7],address_b[6],address_b[5],address_b[4],address_b[3],address_b[2],address_b[1],address_b[0]}),
	.portbbyteenamasks(1'b1),
	.portadataout(),
	.portbdataout(ram_block7a0_PORTBDATAOUT_bus),
	.eccstatus(),
	.dftout());
defparam ram_block7a0.clk0_core_clock_enable = "ena0";
defparam ram_block7a0.clk1_output_clock_enable = "ena1";
defparam ram_block7a0.data_interleave_offset_in_bits = 1;
defparam ram_block7a0.data_interleave_width_in_bits = 1;
defparam ram_block7a0.logical_ram_name = "cntrl_fifo_fifo_181_gccfdha:fifo_0|dcfifo:dcfifo_component|dcfifo_t412:auto_generated|altsyncram_j7a1:fifo_ram|ALTSYNCRAM";
defparam ram_block7a0.mixed_port_feed_through_mode = "dont_care";
defparam ram_block7a0.operation_mode = "dual_port";
defparam ram_block7a0.port_a_address_clear = "none";
defparam ram_block7a0.port_a_address_width = 8;
defparam ram_block7a0.port_a_data_out_clear = "none";
defparam ram_block7a0.port_a_data_out_clock = "none";
defparam ram_block7a0.port_a_data_width = 1;
defparam ram_block7a0.port_a_first_address = 0;
defparam ram_block7a0.port_a_first_bit_number = 0;
defparam ram_block7a0.port_a_last_address = 255;
defparam ram_block7a0.port_a_logical_ram_depth = 256;
defparam ram_block7a0.port_a_logical_ram_width = 1;
defparam ram_block7a0.port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block7a0.port_b_address_clear = "none";
defparam ram_block7a0.port_b_address_clock = "clock1";
defparam ram_block7a0.port_b_address_width = 8;
defparam ram_block7a0.port_b_data_out_clear = "none";
defparam ram_block7a0.port_b_data_out_clock = "clock1";
defparam ram_block7a0.port_b_data_width = 1;
defparam ram_block7a0.port_b_first_address = 0;
defparam ram_block7a0.port_b_first_bit_number = 0;
defparam ram_block7a0.port_b_last_address = 255;
defparam ram_block7a0.port_b_logical_ram_depth = 256;
defparam ram_block7a0.port_b_logical_ram_width = 1;
defparam ram_block7a0.port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam ram_block7a0.port_b_read_enable_clock = "clock1";
defparam ram_block7a0.ram_block_type = "auto";

endmodule

module cntrl_fifo_cmpr_9n5 (
	counter1a6,
	dffe10a_6,
	data_wire_0)/* synthesis synthesis_greybox=0 */;
input 	counter1a6;
input 	dffe10a_6;
output 	data_wire_0;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



twentynm_lcell_comb \data_wire[0]~0 (
	.dataa(!counter1a6),
	.datab(!dffe10a_6),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(data_wire_0),
	.sumout(),
	.cout(),
	.shareout());
defparam \data_wire[0]~0 .extended_lut = "off";
defparam \data_wire[0]~0 .lut_mask = 64'h6666666666666666;
defparam \data_wire[0]~0 .shared_arith = "off";

endmodule

module cntrl_fifo_cmpr_9n5_1 (
	dffe10a_6,
	rdptr_g_6,
	data_wire_0)/* synthesis synthesis_greybox=0 */;
input 	dffe10a_6;
input 	rdptr_g_6;
output 	data_wire_0;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



twentynm_lcell_comb \data_wire[0]~0 (
	.dataa(!dffe10a_6),
	.datab(!rdptr_g_6),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(data_wire_0),
	.sumout(),
	.cout(),
	.shareout());
defparam \data_wire[0]~0 .extended_lut = "off";
defparam \data_wire[0]~0 .lut_mask = 64'h6666666666666666;
defparam \data_wire[0]~0 .shared_arith = "off";

endmodule

module cntrl_fifo_cmpr_9n5_2 (
	counter4a6,
	dffe10a_6,
	data_wire_0)/* synthesis synthesis_greybox=0 */;
input 	counter4a6;
input 	dffe10a_6;
output 	data_wire_0;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



twentynm_lcell_comb \data_wire[0]~0 (
	.dataa(!counter4a6),
	.datab(!dffe10a_6),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(data_wire_0),
	.sumout(),
	.cout(),
	.shareout());
defparam \data_wire[0]~0 .extended_lut = "off";
defparam \data_wire[0]~0 .lut_mask = 64'h6666666666666666;
defparam \data_wire[0]~0 .shared_arith = "off";

endmodule

module cntrl_fifo_cmpr_9n5_3 (
	wrptr_g_6,
	dffe10a_6,
	data_wire_0)/* synthesis synthesis_greybox=0 */;
input 	wrptr_g_6;
input 	dffe10a_6;
output 	data_wire_0;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;



twentynm_lcell_comb \data_wire[0]~0 (
	.dataa(!wrptr_g_6),
	.datab(!dffe10a_6),
	.datac(gnd),
	.datad(gnd),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(data_wire_0),
	.sumout(),
	.cout(),
	.shareout());
defparam \data_wire[0]~0 .extended_lut = "off";
defparam \data_wire[0]~0 .lut_mask = 64'h6666666666666666;
defparam \data_wire[0]~0 .shared_arith = "off";

endmodule

module cntrl_fifo_mux_ij7 (
	int_rdempty,
	counter1a0,
	counter1a1,
	counter1a2,
	counter1a3,
	counter1a4,
	dffe10a_4,
	dffe10a_2,
	dffe10a_3,
	dffe10a_0,
	dffe10a_1,
	rdptr_g_4,
	rdptr_g_2,
	rdptr_g_3,
	rdptr_g_0,
	rdptr_g_1,
	l1_w0_n0_mux_dataout,
	rdreq)/* synthesis synthesis_greybox=0 */;
input 	int_rdempty;
input 	counter1a0;
input 	counter1a1;
input 	counter1a2;
input 	counter1a3;
input 	counter1a4;
input 	dffe10a_4;
input 	dffe10a_2;
input 	dffe10a_3;
input 	dffe10a_0;
input 	dffe10a_1;
input 	rdptr_g_4;
input 	rdptr_g_2;
input 	rdptr_g_3;
input 	rdptr_g_0;
input 	rdptr_g_1;
output 	l1_w0_n0_mux_dataout;
input 	rdreq;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \l1_w0_n0_mux_dataout~0_combout ;
wire \l1_w0_n0_mux_dataout~1_combout ;
wire \l1_w0_n0_mux_dataout~2_combout ;
wire \l1_w0_n0_mux_dataout~3_combout ;


twentynm_lcell_comb \l1_w0_n0_mux_dataout~4 (
	.dataa(!int_rdempty),
	.datab(!rdreq),
	.datac(!\l1_w0_n0_mux_dataout~0_combout ),
	.datad(!\l1_w0_n0_mux_dataout~1_combout ),
	.datae(!\l1_w0_n0_mux_dataout~2_combout ),
	.dataf(!\l1_w0_n0_mux_dataout~3_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(l1_w0_n0_mux_dataout),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~4 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~4 .lut_mask = 64'hFFFDFFFDFFFD2220;
defparam \l1_w0_n0_mux_dataout~4 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~0 (
	.dataa(!counter1a2),
	.datab(!counter1a3),
	.datac(!counter1a4),
	.datad(!dffe10a_4),
	.datae(!dffe10a_2),
	.dataf(!dffe10a_3),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~0 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~0 .lut_mask = 64'h8008400420021001;
defparam \l1_w0_n0_mux_dataout~0 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~1 (
	.dataa(!counter1a0),
	.datab(!counter1a1),
	.datac(!dffe10a_0),
	.datad(!dffe10a_1),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~1 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~1 .lut_mask = 64'h4812481248124812;
defparam \l1_w0_n0_mux_dataout~1 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~2 (
	.dataa(!dffe10a_4),
	.datab(!dffe10a_2),
	.datac(!dffe10a_3),
	.datad(!rdptr_g_4),
	.datae(!rdptr_g_2),
	.dataf(!rdptr_g_3),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~2_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~2 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~2 .lut_mask = 64'h8040201008040201;
defparam \l1_w0_n0_mux_dataout~2 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~3 (
	.dataa(!dffe10a_0),
	.datab(!dffe10a_1),
	.datac(!rdptr_g_0),
	.datad(!rdptr_g_1),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~3_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~3 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~3 .lut_mask = 64'h8421842184218421;
defparam \l1_w0_n0_mux_dataout~3 .shared_arith = "off";

endmodule

module cntrl_fifo_mux_ij7_1 (
	int_rdempty,
	counter1a5,
	counter1a7,
	counter1a8,
	data_wire_0,
	data_wire_01,
	dffe10a_7,
	dffe10a_8,
	dffe10a_5,
	rdptr_g_7,
	rdptr_g_8,
	rdptr_g_5,
	l1_w0_n0_mux_dataout,
	rdreq)/* synthesis synthesis_greybox=0 */;
input 	int_rdempty;
input 	counter1a5;
input 	counter1a7;
input 	counter1a8;
input 	data_wire_0;
input 	data_wire_01;
input 	dffe10a_7;
input 	dffe10a_8;
input 	dffe10a_5;
input 	rdptr_g_7;
input 	rdptr_g_8;
input 	rdptr_g_5;
output 	l1_w0_n0_mux_dataout;
input 	rdreq;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \l1_w0_n0_mux_dataout~0_combout ;
wire \l1_w0_n0_mux_dataout~1_combout ;


twentynm_lcell_comb \l1_w0_n0_mux_dataout~2 (
	.dataa(!int_rdempty),
	.datab(!rdreq),
	.datac(!data_wire_0),
	.datad(!data_wire_01),
	.datae(!\l1_w0_n0_mux_dataout~0_combout ),
	.dataf(!\l1_w0_n0_mux_dataout~1_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(l1_w0_n0_mux_dataout),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~2 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~2 .lut_mask = 64'hFFFFDFDF22FF02DF;
defparam \l1_w0_n0_mux_dataout~2 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~0 (
	.dataa(!counter1a5),
	.datab(!counter1a7),
	.datac(!counter1a8),
	.datad(!dffe10a_7),
	.datae(!dffe10a_8),
	.dataf(!dffe10a_5),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~0 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~0 .lut_mask = 64'h8020080240100401;
defparam \l1_w0_n0_mux_dataout~0 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~1 (
	.dataa(!dffe10a_7),
	.datab(!dffe10a_8),
	.datac(!dffe10a_5),
	.datad(!rdptr_g_7),
	.datae(!rdptr_g_8),
	.dataf(!rdptr_g_5),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~1 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~1 .lut_mask = 64'h8040201008040201;
defparam \l1_w0_n0_mux_dataout~1 .shared_arith = "off";

endmodule

module cntrl_fifo_mux_ij7_2 (
	int_wrfull,
	wrptr_g_0,
	wrptr_g_1,
	wrptr_g_2,
	wrptr_g_3,
	wrptr_g_4,
	counter4a4,
	dffe10a_4,
	counter4a2,
	dffe10a_2,
	counter4a3,
	dffe10a_3,
	counter4a0,
	dffe10a_0,
	counter4a1,
	dffe10a_1,
	l1_w0_n0_mux_dataout,
	wrreq)/* synthesis synthesis_greybox=0 */;
input 	int_wrfull;
input 	wrptr_g_0;
input 	wrptr_g_1;
input 	wrptr_g_2;
input 	wrptr_g_3;
input 	wrptr_g_4;
input 	counter4a4;
input 	dffe10a_4;
input 	counter4a2;
input 	dffe10a_2;
input 	counter4a3;
input 	dffe10a_3;
input 	counter4a0;
input 	dffe10a_0;
input 	counter4a1;
input 	dffe10a_1;
output 	l1_w0_n0_mux_dataout;
input 	wrreq;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \l1_w0_n0_mux_dataout~0_combout ;
wire \l1_w0_n0_mux_dataout~1_combout ;
wire \l1_w0_n0_mux_dataout~2_combout ;
wire \l1_w0_n0_mux_dataout~3_combout ;


twentynm_lcell_comb \l1_w0_n0_mux_dataout~4 (
	.dataa(!int_wrfull),
	.datab(!wrreq),
	.datac(!\l1_w0_n0_mux_dataout~0_combout ),
	.datad(!\l1_w0_n0_mux_dataout~1_combout ),
	.datae(!\l1_w0_n0_mux_dataout~2_combout ),
	.dataf(!\l1_w0_n0_mux_dataout~3_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(l1_w0_n0_mux_dataout),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~4 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~4 .lut_mask = 64'h000200020002DDDF;
defparam \l1_w0_n0_mux_dataout~4 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~0 (
	.dataa(!counter4a4),
	.datab(!dffe10a_4),
	.datac(!counter4a2),
	.datad(!dffe10a_2),
	.datae(!counter4a3),
	.dataf(!dffe10a_3),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~0 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~0 .lut_mask = 64'h9009000000009009;
defparam \l1_w0_n0_mux_dataout~0 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~1 (
	.dataa(!counter4a0),
	.datab(!dffe10a_0),
	.datac(!counter4a1),
	.datad(!dffe10a_1),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~1 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~1 .lut_mask = 64'h6006600660066006;
defparam \l1_w0_n0_mux_dataout~1 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~2 (
	.dataa(!wrptr_g_2),
	.datab(!wrptr_g_3),
	.datac(!wrptr_g_4),
	.datad(!dffe10a_4),
	.datae(!dffe10a_2),
	.dataf(!dffe10a_3),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~2_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~2 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~2 .lut_mask = 64'h8008400420021001;
defparam \l1_w0_n0_mux_dataout~2 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~3 (
	.dataa(!wrptr_g_0),
	.datab(!wrptr_g_1),
	.datac(!dffe10a_0),
	.datad(!dffe10a_1),
	.datae(gnd),
	.dataf(gnd),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~3_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~3 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~3 .lut_mask = 64'h8421842184218421;
defparam \l1_w0_n0_mux_dataout~3 .shared_arith = "off";

endmodule

module cntrl_fifo_mux_ij7_3 (
	int_wrfull,
	wrptr_g_5,
	wrptr_g_8,
	wrptr_g_7,
	data_wire_0,
	data_wire_01,
	counter4a7,
	dffe10a_7,
	counter4a8,
	dffe10a_8,
	counter4a5,
	dffe10a_5,
	l1_w0_n0_mux_dataout,
	wrreq)/* synthesis synthesis_greybox=0 */;
input 	int_wrfull;
input 	wrptr_g_5;
input 	wrptr_g_8;
input 	wrptr_g_7;
input 	data_wire_0;
input 	data_wire_01;
input 	counter4a7;
input 	dffe10a_7;
input 	counter4a8;
input 	dffe10a_8;
input 	counter4a5;
input 	dffe10a_5;
output 	l1_w0_n0_mux_dataout;
input 	wrreq;

wire gnd;
wire vcc;
wire unknown;

assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;

wire \l1_w0_n0_mux_dataout~0_combout ;
wire \l1_w0_n0_mux_dataout~1_combout ;


twentynm_lcell_comb \l1_w0_n0_mux_dataout~2 (
	.dataa(!int_wrfull),
	.datab(!wrreq),
	.datac(!data_wire_0),
	.datad(!data_wire_01),
	.datae(!\l1_w0_n0_mux_dataout~0_combout ),
	.dataf(!\l1_w0_n0_mux_dataout~1_combout ),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(l1_w0_n0_mux_dataout),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~2 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~2 .lut_mask = 64'h00002020DD00FD20;
defparam \l1_w0_n0_mux_dataout~2 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~0 (
	.dataa(!counter4a7),
	.datab(!dffe10a_7),
	.datac(!counter4a8),
	.datad(!dffe10a_8),
	.datae(!counter4a5),
	.dataf(!dffe10a_5),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~0_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~0 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~0 .lut_mask = 64'h0660000000000660;
defparam \l1_w0_n0_mux_dataout~0 .shared_arith = "off";

twentynm_lcell_comb \l1_w0_n0_mux_dataout~1 (
	.dataa(!wrptr_g_5),
	.datab(!wrptr_g_8),
	.datac(!wrptr_g_7),
	.datad(!dffe10a_7),
	.datae(!dffe10a_8),
	.dataf(!dffe10a_5),
	.datag(gnd),
	.cin(gnd),
	.sharein(gnd),
	.combout(\l1_w0_n0_mux_dataout~1_combout ),
	.sumout(),
	.cout(),
	.shareout());
defparam \l1_w0_n0_mux_dataout~1 .extended_lut = "off";
defparam \l1_w0_n0_mux_dataout~1 .lut_mask = 64'h0220088001100440;
defparam \l1_w0_n0_mux_dataout~1 .shared_arith = "off";

endmodule
