	component dp_32bit is
		port (
			data      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- datain
			wraddress : in  std_logic_vector(11 downto 0) := (others => 'X'); -- wraddress
			rdaddress : in  std_logic_vector(11 downto 0) := (others => 'X'); -- rdaddress
			wren      : in  std_logic                     := 'X';             -- wren
			wrclock   : in  std_logic                     := 'X';             -- wrclock
			rdclock   : in  std_logic                     := 'X';             -- rdclock
			q         : out std_logic_vector(31 downto 0)                     -- dataout
		);
	end component dp_32bit;

	u0 : component dp_32bit
		port map (
			data      => CONNECTED_TO_data,      --  ram_input.datain
			wraddress => CONNECTED_TO_wraddress, --           .wraddress
			rdaddress => CONNECTED_TO_rdaddress, --           .rdaddress
			wren      => CONNECTED_TO_wren,      --           .wren
			wrclock   => CONNECTED_TO_wrclock,   --           .wrclock
			rdclock   => CONNECTED_TO_rdclock,   --           .rdclock
			q         => CONNECTED_TO_q          -- ram_output.dataout
		);

